ARM Processor Instruction Set

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ARM Processor Instruction Set 5.6.4 Assembler syntax where: MUL{cond}{S} Rd,Rm,Rs MLA{cond}{S} Rd,Rm,Rs,Rn {cond} two-character condition mnemonic, see ➲Figure 5-2: Condition codes on page 5-3 {S} Rd, Rm, Rs, Rn set condition codes if S present are expressions evaluating to a register number other than R15. 5.6.5 Examples MUL R1,R2,R3 ;R1:=R2*R3 MLAEQS R1,R2,R3,R4 ;conditionally ;R1:=R2*R3+R4, ;setting condition codes Preliminary - Unrestricted 5-22 ARM7500 Data Sheet ARM DDI 0050C
5.7 Single data transfer (LDR, STR) ARM Processor Instruction Set The instruction is only executed if the condition is true. The various conditions are defined at the beginning of this chapter. The instruction encoding is shown in ➲Figure 5-14: Single data transfer instructions. The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register. The result of this calculation may be written back into the base register if ’auto-indexing' is required. 31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0 Cond 01 I P U B W L Rn Rd Offset Source/Destination register Base register Load/Store bit 0 = Store to memory 1 = Load from memory Write-back bit 0 = no write-back 1 = write address into base Byte/Word bit 0 = transfer word quantity 1 = transfer byte quantity Up/Down bit 0 = down; subtract offset from base 1 = up; add offset to base Pre/Post indexing bit 0 = post; add offset after transfer 1 = pre; add offset before transfer Immediate offset 0 = offset is an immediate value 11 Immediate offset Unsigned 12 bit immediate offset 1 = offset is a register 11 4 3 0 Shift Rm 0 Preliminary - Unrestricted shift applied to Rm Condition field Offset register Figure 5-14: Single data transfer instructions ARM7500 Data Sheet ARM DDI 0050C 5-23
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Page 9 and 10: If the S bit is set (and Rd is not
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Page 29 and 30: 5.8 Block data transfer (LDM, STM)
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Page 49 and 50: 5.14.2 Transfers to R15 5.14.3 Tran
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ARM Processor Instruction Set

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