ARM Processor Instruction Set

ARM Processor Instruction Set
5.13.5 Data aborts
5.13.6 Instruction cycle times
5.13.7 Assembler syntax
If the address is legal but the memory manager generates an abort, the data trap will
be taken. The write-back of the modified base will take place, but all other processor
state will be preserved. The coprocessor is partly responsible for ensuring that the
data transfer can be restarted after the cause of the abort has been resolved, and must
ensure that any subsequent actions it undertakes can be repeated when the
instruction is retried.
All LDC instructions are emulated in software: the number of cycles taken will depend
on the coprocessor support software.
{cond}{L} p#,cd,
Preliminary - Unrestricted
LDC
STC
{L}
{cond}
load from memory to coprocessor
store from coprocessor to memory
when present perform long transfer (N=1), otherwise perform short
transfer (N=0)
two character condition mnemonic, see ➲Figure 5-2: Condition codes
on page 5-3
p# the unique number of the required coprocessor
cd
can be:
is an expression evaluating to a valid coprocessor register number
that is placed in the CRd field
1 An expression which generates an address:
The assembler will attempt to generate an instruction using the PC as a base
and a corrected immediate offset to address the location given by evaluating
the expression. This will be a PC relative, pre-indexed address. If the address
is out of range, an error will be generated.
2 A pre-indexed addressing specification:
[Rn]
[Rn,]{!}
offset of zero
offset of bytes
3 A post-indexed addressing specification:
Rn
[Rn],
offset of bytes
is an expression evaluating to a valid processor register number.
Note, if Rn is R15 then the assembler will subtract 8 from the offset
value to allow for processor pipelining.
{!} write back the base register (set the W bit) if ! is present
5-46
ARM7500 Data Sheet
ARM DDI 0050C