ARM Processor Instruction Set

More documents

Recommendations

Info

ARM Processor Instruction Set 5.10.5 Examples SWI ReadC ;get next character from read stream SWI WriteI+”k” ;output a “k” to the write stream SWINE 0 ;conditionally call supervisor ;with 0 in comment field The above examples assume that suitable supervisor code exists, for instance: 0x08 B Supervisor ;SWI entry point EntryTable ;addresses of supervisor routines DCD ZeroRtn DCD ReadCRtn DCD WriteIRtn ... Zero EQU 0 ReadC EQU 256 WriteI EQU 512 Preliminary - Unrestricted Supervisor ;SWI has routine required in bits 8-23 and data (if any) in bits ;0-7. ;Assumes R13_svc points to a suitable stack STMFD R13,{R0-R2,R14}; save work registers and return address LDR R0,[R14,#-4] ;get SWI instruction BIC R0,R0,#0xFF000000; ;clear top 8 bits MOV R1,R0,LSR#8 ;get routine offset ADR R2,EntryTable ;get start address of entry table LDR R15,[R2,R1,LSL#2]; ;branch to appropriate routine WriteIRtn ;enter with character in R0 bits 0-7 . . . . . . LDMFD R13,{R0-R2,R15}^; ;restore workspace and return ; restoring processor mode and flags 5-40 ARM7500 Data Sheet ARM DDI 0050C
ARM Processor Instruction Set 5.11 Coprocessor Instructions on the ARM Processor The core ARM processor in the ARM7500, unlike some other ARM processors, does not have an external coprocessor interface. It only supports a single on-chip coprocessor, #15, which is used to program the on-chip control registers. This only supports the Coprocessor Register Transfer instructions (MRC and MCR). All other coprocessor instructions will cause the undefined instruction trap to be taken on the ARM processor. These coprocessor instructions can be emulated in software by the undefined trap handler. Even though external coprocessors cannot be connected to the ARM processor, the coprocessor instructions are still described here in full for completeness. It must be kept in mind that any external coprocessor referred to will be a software emulation. Preliminary - Unrestricted ARM7500 Data Sheet ARM DDI 0050C 5-41
Page 1 and 2: 1 11 5 ARM Processor Instruction Se
Page 3 and 4: ARM Processor Instruction Set 5.2 T
Page 5 and 6: ARM Processor Instruction Set 5.3.3
Page 7 and 8: ARM Processor Instruction Set . 31
Page 9 and 10: If the S bit is set (and Rd is not
Page 11 and 12: ARM Processor Instruction Set 31 30
Page 15 and 16: ARM Processor Instruction Set 5.5 P
Page 23 and 24: 5.7 Single data transfer (LDR, STR)
Page 25 and 26: ARM Processor Instruction Set Littl
Page 29 and 30: 5.8 Block data transfer (LDM, STM)
Page 31 and 32: ARM Processor Instruction Set 0x100
Page 37 and 38: ARM Processor Instruction Set 5.9 S
Page 39: ARM Processor Instruction Set 5.10
Page 43 and 44: ARM Processor Instruction Set 5.12.
Page 49 and 50: 5.14.2 Transfers to R15 5.14.3 Tran
Page 51 and 52: ARM Processor Instruction Set 5.15
Page 53 and 54: ARM Processor Instruction Set BCC D
Page 55 and 56: ARM Processor Instruction Set ; Not
Page 57 and 58: ARM Processor Instruction Set • a

ARM Processor Instruction Set

Create successful ePaper yourself

Delete template?

Save as template?