ARM Processor Instruction Set

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ARM Processor Instruction Set 5.5.4 Assembler syntax where: 1 MRS - transfer PSR contents to a register MRS{cond} Rd, 2 MSR - transfer register contents to PSR MSR{cond} ,Rm 3 MSR - transfer register contents to PSR flag bits only MSR{cond} ,Rm The most significant four bits of the register contents are written to the N,Z,C & V flags respectively. 4 MSR - transfer immediate value to PSR flag bits only MSR{cond} , The expression should symbolise a 32-bit value of which the most significant four bits are written to the N,Z,C & V flags respectively. Preliminary - Unrestricted {cond} two-character condition mnemonic, see ➲Figure 5-2: Condition codes on page 5-3 Rd and Rm are expressions evaluating to a register number other than R15 is CPSR, CPSR_all, SPSR or SPSR_all. (CPSR and CPSR_all are synonyms as are SPSR and SPSR_all) is CPSR_flg or SPSR_flg where used, the assembler will attempt to generate a shifted immediate 8-bit field to match the expression. If this is impossible, it will give an error. 5-18 ARM7500 Data Sheet ARM DDI 0050C
ARM Processor Instruction Set 5.5.5 Examples In User mode the instructions behave as follows: MSR CPSR_all,Rm ;CPSR[31:28]
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Page 9 and 10: If the S bit is set (and Rd is not
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Page 23 and 24: 5.7 Single data transfer (LDR, STR)
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Page 29 and 30: 5.8 Block data transfer (LDM, STM)
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Page 49 and 50: 5.14.2 Transfers to R15 5.14.3 Tran
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ARM Processor Instruction Set

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