Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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Digital Subscriber Line Access Multiplexer (DSLAM) Example Design 2.2 Dual Chip Data Flow Figure 4 illustrates what steps are necessary to move an IP packet from the ATM/DSL Aggregator to the output of the Receive Processor, which goes to the IXB3208. Figure 4. Receive Processor Data Flow for ATM AAL5 PDUs DSLAM / ATM PDU on Rx Port (and subsequently in the RFIFO) Note: Only steps 1 through 4 are performed for middle cells in the PDU 1 Receive DSLAM ATM Cell DSLAM HDR ATM HDR If last cell in PDU PAD CLP UU LEN CRC DSLAM HDR ATM HDR If first cell in PDU LLC HDR IP HDR TCP HDR Payload 9 Check AAL5 Trailer (length and checksum) 2 Look up VC (using hash) 5 Validate AAL5 and IP Headers 4 Move cell payload to buffer SDRAM Packet Buffer Used for computing new header (32 bytes) Cell 0 (48 Bytes) Cell 1 (48 Bytes) Cell N (48 Bytes) 7 Create new header in buffer Connection Table VP/VC/Physical Port Number 6 Look up route and header on first cell Route Table Destination IP/IP Port Connection Status Bit Rate Network Model Queue ID Header Info Destination Port / VC 8 Update with new header info Buffer Base AAL5 Header Buffer Offset 3 Locate buffer and offset 10 Transmit in 64-byte segments with prepended Intel® IXB3208 Network Processor headers A9559-01 10 Application Note
Digital Subscriber Line Access Multiplexer (DSLAM) Example Design Figure 5 illustrates what steps are necessary to move a flow control packet from the ATM DSL Aggregator to the output of the Receive Processor, which goes to the IXB3208. Figure 5. Receive Processor Data Flow for Flow Control Packets DSLAM Flow Control Packet on Rx Port (and subsequently in the RFIFO) 1 Receive DSLAM Flow Control Packet DSLAM HDR Payload 2 Allocate new buffer in SDRAM SDRAM Packet Buffer Flow Control Packet 3 Move payload to buffer 4 Transmit in 64-byte segments with prepended Intel® IXB3208 Network Processor and Inter-IXP headers A9560-01 On the data path in the Receive Processor, flow control packets coming from the ATM/DSL Aggregator over the ATM port are transmitted over the IX bus with an appropriate Inter-IXP header and segmented for IXB3208 consumption. No transformation is performed on flow control packets in the Receive Processor. Application Note 11
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Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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