Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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Digital Subscriber Line Access Multiplexer (DSLAM) Example Design 3.5 Transmit Processor Traffic Shaper The TM4.1_Shaper function reads a single entry in the calendar queue. Each entry has room to contain a must-send VC index (associated with a VC configured as CBR @ PCR or VBR-rt @ SCR), a could-send VC index (associated with a VC configured as VBR-rt @ PCR or VBR-nrt @SCR) and an unshaped VC index (associated with a VC configured as VBR-nrt @ PCR or UBR). The VC indices that will be processed at any given time are prioritized in the order as they appear - must-send/could-send/unshaped. If multiple VC indices are present in an entry, the VC index with the highest priority gets processed. All other VC indices are re-scheduled without transmitting a cell on such VCs. After transmitting a cell, the next cell in that VC’s queue will be requested to be scheduled. If a VP/VC index is not found in an entry, the shaper will wait for the duration (inter-cell gap + time it takes to process a cell for a given bandwidth). 3.6 Transmit Processor Traffic Transmit The ATM transmit function is passed a VC index and port number. If the VC index indicates to do a port skip (no data for the port is available to be transmitted) then a port skip is done and the transmit buffer element is updated for the next cell. If flow control is asserted for the port, then a port skip is done and the transmit buffer element is updated for the next cell. A packet is de-queued from the VC queue. The packet descriptor is then read. The fabric and cell header is generated and put into the transmit buffer. The CRC is run on the packet data for this cell and put into the transmit buffer. If this is the last cell, then the packet trailer is generated and also put into the transmit buffer. The packet is then transmitted and the transmit buffer element is updated for the next cell. Next, a check is made with the number of cells en-queued for the VC and the lower queue threshold for that VC. If they are equal or the cells en-queued is less than the said threshold, a flow control message is sent onto the ready bus indicating to de-assert flow control. The number of cells en-queued is then decremented. If this is the last cell of a packet, the packet buffer is put back onto the free list of packet buffers. 4.0 Data and Tables 4.1 Receive Processor 4.1.1 Input Data This section describes data input to and output from the Receive Processor in the DSLAM Example Design. Two types of packets may be input to the Receive Processor: • Data Packets • Flow Control Packets Data packets consist of RFC1483-compliant AAL5 PDUs which have been segmented into ATM cells and prepended with a custom header. 22 Application Note
Digital Subscriber Line Access Multiplexer (DSLAM) Example Design Flow control packets consist of a single unsegmented data packet (having a length of two octets) prepended with the same custom header that was prepended to the ATM cells comprising the data packets. This custom header contains three pieces of information: • Whether the packet is data or flow control • The type of physical port from which the packet was received (e.g. ATM, Frame Relay, Ethernet, etc.). • The port number of the physical port from which the packet was received (0-2047). Application Note 23
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Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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