Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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Digital Subscriber Line Access Multiplexer (DSLAM) Example Design Figure 6 illustrates what steps are necessary to move IP packets and flow control packets from the IXB3208 input to the Transmit Processor to the ATM port. Figure 6. Transmit Processor Data Flow for PDUs and Flow Control Pre-classified DSLAM / ATM PDU on Rx Port (and subsequently in the RFIFO) 1 Receive Intel® IXB3208 segment Note: Only steps 1 and 3 are conducted for middle segments in the PDU If last 64-byte or partial 64-byte segment in PDU (if EOP is true) Payload If first 64-byte segment in PDU (if SOP is true) Inter-IXP Header Payload 4 Move segment payload to buffer 2 Store Inter-IXP header in thread mailbox 3 Move segment payload to buffer SDRAM Packet Buffer Segment 0 (64 bytes) Segment 1 (64 bytes) Segment 2 (64 bytes) Thread Mailbox (contains Inter-IXP header) Queue for Traffic Management 5 Retrieve Inter-IXP header and queue to traffic management Segment n (64 bytes or less) 6 OR If PDU, Traffic Management schedules, shapes and transmits AAL5 PDU as ATM cells with DSLAM header per the contract specified in the Inter-IXP header 7 If flow control, Receive code blocks or unblocks transmission based on port and flow ID in Inter-IXP header. A9562-01 In the Transmit Processor, data is received from the IXB3208 in 64-byte (or less) segments. The last segment may not be 64 bytes, depending on the length of the PDU or flow control packet. The first segment contains the Inter-IXP header attached by the Receive Processor. This header contains information that classifies the packet: • Data or Flow Control • Protocol (ATM or other) • Unicast or Multicast 12 Application Note
Digital Subscriber Line Access Multiplexer (DSLAM) Example Design • The bit rate at which the data should be sent (CBR/VBR/UBR) • The UBR Priority • Time spent in Receive Processor • Packet Size • Queue ID, Output Port, and VC The packet is stored in SDRAM. The Inter-IXP header is saved to a mailbox in scratch memory until the entire packet is received, and then it is queued to the traffic management software. The traffic management software uses information from the Inter-IXP header, vc table, and port table for scheduling, shaping, and transmission of the packet stored in SDRAM. Information regarding the traffic management software design may be found on page 42 of the DSLAM Router/Traffic Shaper Software Design Specification White Paper. 2.3 StrongARM Core Initialization Before starting the microengines, the Receive Processor StrongARM Core initializes the IP Lookup (Routing) Table, and the VP/VC Lookup (Connection) Table. It also initializes the Buffer Descriptor Freelist. On the Transmit Processor, the StrongARM Core initializes the Rate Manager (see Section 4.3.1). In the simulation environment, this is done by code invoked from the Transactor startup scripts dslam_proc_a.ind and dslam_proc_b.ind. The IP and VC table management software are emulated with a combination of Transactor foreign models and interpreted Transactor scripts. 2.4 Microengine Initialization In the Receive Processor, the initialization code of the transmit microblock group on Microengine 5, thread 0, performs most of the initialization for the Receive Processor in general. It also signals the appropriate threads on Microengines 0-3, which start the receive microblock group. In the Transmit Processor, dslam_uc_init and dslam_system_init initialize the entire application. Application Note 13
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Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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