Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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Digital Subscriber Line Access Multiplexer (DSLAM) Example Design 4.2 Transmit Processor 4.2.1 Input Data This section describes data input to and output from the Transmit Processor in the DSLAM Example Design. Data packets and flow control packets are input to the Transmit Processor from the Receive Processor through the IXB3208 chip. The only difference between the output of the Receive Processor and the input to the Transmit Processor is that the IXB3208 headers, which were prepended to each of the packet segments, have been removed by the IXB3208. Figure 15 shows how PDUs and flow control packets output from the Receive Processor to the IXB3208 are stripped of the IXB3208 headers and then input to the Transmit Processor. Figure 15. Transmit Processor Input from IXB3208 Intel ® IXB3208 Input (Processor A output) Intel IXB3208 Header Payload 64 bytes Intel IXB3208 Header Payload 64 bytes Intel IXB3208 Header Payload 64 bytes Intel IXB3208 Output (Processor B input) Payload 64 bytes Payload 64 bytes Payload 64 bytes 28 Application Note
Digital Subscriber Line Access Multiplexer (DSLAM) Example Design 4.2.2 Output Data Data packets output from the Transmit Processor consist of RFC1483-compliant AAL5 PDUs which have been segmented into ATM cells and prepended with a custom header. Figure 16 shows how PDUs are completed, segmented, and output from the Transmit Processor to the DSL Aggregator with the prepended custom DSLAM header, just as it was input to the Receive Processor. Figure 16. Transmit Processor Output Processor B Input Payload 64 bytes Payload 64 bytes Payload 64 bytes Reassembly Inter-IXP Header AAL5 PDU AAL5 CS CS-SDU Info Field Padding 0-47 bytes UU 1 byte CPI 1 byte Length 2 bytes CRC 4 bytes SAR Sub-Layer ATM Cell Header Payload 48 bytes ATM Cell Header Payload 48 bytes ATM Cell Header Payload 48 bytes DSLAM (output to Processor B) DSLAM Header 4 bytes ATM Cell 53 bytes DSLAM Header 4 bytes ATM Cell 53 bytes Packet Type 1 bit Unused 18 bits Physical Port Number 11 bits Physical Port Type 2 bits A9558-01 4.3 Connection, Routing, and Hash Tables The Receive Processor contains two primary tables: • Connection Table • Routing Table The connection table is accessed by using a pre-computed hash table and algorithm. The ATM VP (virtual path), VC (virtual channel), and physical port numbers contained in the input custom header are used to create a hash key that is then used to look up the connection entry in the table. Each entry in the connection table contains the following: • Status of the ATM virtual circuit (VP/VC) Application Note 29
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Page 3 and 4: Contents Contents 1.0 Introduction
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Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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