Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

Digital Subscriber Line Access Multiplexer (DSLAM) Example Design
2.0 System Overview
Figure 1 illustrates the steps for moving an IP packet from the ATM/DSL Aggregator to the output
of the Transmit Processor.
Figure 1. System Overview
Intel ® Pentium ®
Processor
PCI Bus
Intel ® IXP1200
"Receive
Processor"
Reassembly
Validation
IP Lookup
Protocol Translation
Classification
Intel ® IX Bus
Intel ® IXB3208
Network
Processor
Intel IX Bus
Intel IXP1200
"Transmit
Processor"
Traffic Management
Segmentation
Transmission
Incoming
"DSLAM ATM"
Traffic
Outgoing
"DSLAM ATM"
Traffic
Customer-provided
ATM/DSL Aggregator
ATM
DSL
A9550-01
On the data path in the Receive Processor, IP over ATM traffic (coming from the ATM/DSL
aggregator over the ATM port) is processed and transmitted over the IX bus as a pre-classified
AAL5 PDU segmented for IXB3208 consumption. The receiving threads receive ATM cells with
prepended DSLAM headers, perform reassembly of the ATM PDU, and extract the IP packet
according to the AAL5 and LLC/SNAP specified in a VC connection table.
Upon reception of a complete AAL5 PDU, the receiving threads (if so configured) use the
hardware CRC capability of the IXP1240 to perform the CRC-32 checks necessary for AAL5. The
receiving threads perform an IP lookup and any required IP header transformation, prepend an
inter-IXP header containing classification data, and then queue the PDU to the transmit thread.
Application Note 7