Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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Contents 7.1.1 Initialization Scripts ................................................................................................ 32 7.1.2 Test Case Scripts .................................................................................................. 33 7.2 Simulation for the Transmit Processor Project ................................................................... 34 7.2.1 Initialization Scripts ................................................................................................ 34 7.2.2 Test Case Scripts .................................................................................................. 34 7.3 Simulation for the Receive/Transmit Processor Project ..................................................... 36 7.3.1 Initialization Script.................................................................................................. 36 7.3.2 Test Case Scripts .................................................................................................. 36 8.0 Performance ............................................................................................................................ 37 9.0 Limitations ............................................................................................................................... 37 10.0 Extending the Example Design ....................................................................................... 38 11.0 Acronyms & Definitions...................................................................................................... 39 12.0 Reference Documents .........................................................................................................40 Figures 1 System Overview.......................................................................................................................... 7 2 Receive Processor System Partitioning ....................................................................................... 8 3 Transmit Processor System Partitioning ...................................................................................... 9 4 Receive Processor Data Flow for ATM AAL5 PDUs ..................................................................10 5 Receive Processor Data Flow for Flow Control Packets ............................................................11 6 Transmit Processor Data Flow for PDUs and Flow Control ....................................................... 12 7 Receive Processor Receive Microblock Group Data Flow ......................................................... 14 8 Receive Processor Transmit Microblock Group .........................................................................19 9 Transmit Processor Receive Microblock Group .........................................................................20 10 Receive Processor Input - Routed IP over ATM with DSLAM Header ....................................... 24 11 Receive Processor Input - Bridged Ethernet over ATM with DSLAM Headers .......................... 25 12 Receive Processor Input - Flow Control Packet with DSLAM Header ....................................... 26 13 Receive Processor Output to IXB3208....................................................................................... 27 14 Inter-IXP Header Format ............................................................................................................ 27 15 Transmit Processor Input from IXB3208 .................................................................................... 28 16 Transmit Processor Output.........................................................................................................29 Tables 1 L3 Routing Table - IP Route Example ........................................................................................ 30 2 Test Case Descriptions and their Files....................................................................................... 33 3 Test Case Descriptions and their Network Traffic dlls................................................................ 35 4 Test Case Descriptions and their Stream Files .......................................................................... 35 5 Test Case Descriptions and their Files....................................................................................... 37 Application Note
Digital Subscriber Line Access Multiplexer (DSLAM) Example Design 1.0 Introduction Intel develops software example designs to demonstrate the capabilities of the IXP Network Processor Family. This document describes the implementation of example software demonstrating the IXP1240 in a Digital Subscriber Line Access Multiplexer (DSLAM) environment. In particular, this example design uses the IXP1200 to route IP packets between ATM and a DSL Aggregator. This document serves as a companion to the comments in the source code, and is intended to clarify the structure and general workings of the design. The following material is covered: scope of the design; code structure and flow; data structures; inter-process signaling; initialization and startup; software and hardware execution environments; etc. At the end of this document, a list of acronyms and definitions, as well as a list of related documents are provided. The README.TXT bundled with the software should be consulted for instructions on running the project, building the code, and the actual layout of the source files. 1.1 Purpose of DSLAM Example Design This example design is intended as a starting point for customers designing similar applications. It is also intended for customers to get an idea of what the IXP1200 Network Processor is capable of, and what kind of performance can be expected. Users may modify the code, adding additional modules that are proprietary or more specific to their needs, and estimate performance. This Example Design demonstrates just one software architecture in which the IXP1200 can be used in DSLAM-related designs. It should be noted that this design is just a starting point, and not intended to be ’production ready’. 1.2 Scope of Example Design This design addresses the following: • The completed IXP1200 microcode and micro-C shall run on the simulator in the IXP1200 Developer WorkBench (DWB) using the IXP1240 chip setting. • Two-IXP1240-Processor Design (using an IXB3208 as an interconnection device) • One OC-12 port input, one OC-12 port output • Segmentation and Re-assembly (SAR) • ATM Adaptation Layer 5 • IP over ATM LLC/SNAP Encapsulation (RFC 1483) • Routing between ATM and DSL based on IP, supporting both Longest Prefix Match and FiveTuple lookup methods • Constant Bit Rate (CBR), Variable Bit Rate (VBR), and Unspecified Bit Rate (UBR) • Support for up to 4096 Virtual Channels (VC) • Flow Control • Use of “microblock” architecture (Receive Processor) • Use of Micro-C Compiler (Transmit Processor only) Application Note 5
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Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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