Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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Information in this document is provided in connection with Intel ® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Digital Subscriber Line Access Multiplexer (DSLAM) Example Design may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2002 *Other names and brands may be claimed as the property of others.
Contents Contents 1.0 Introduction ...............................................................................................................................5 1.1 Purpose of DSLAM Example Design....................................................................................5 1.2 Scope of Example Design ....................................................................................................5 1.3 Execution Environment.........................................................................................................6 1.3.1 Software...................................................................................................................6 1.3.2 Hardware .................................................................................................................6 2.0 System Overview.....................................................................................................................7 2.1 Software Partitioning.............................................................................................................8 2.2 Dual Chip Data Flow...........................................................................................................10 2.3 StrongARM Core Initialization.............................................................................................13 2.4 Microengine Initialization ....................................................................................................13 3.0 Microengine Functional Blocks.......................................................................................14 3.1 Receive Microblock Group..................................................................................................14 3.1.1 Initialization Microblock..........................................................................................15 3.1.2 Ingress Microblock.................................................................................................15 3.1.3 Transform Microblock ............................................................................................16 3.1.4 Egress Microblock .................................................................................................17 3.2 Receive Processor Transmit Microblock Group .................................................................19 3.3 Transmit Processor Receive Microblock Group .................................................................20 3.3.1 Initialization Microblock..........................................................................................20 3.3.2 Ingress Microblock.................................................................................................20 3.3.3 Transform Microblocks...........................................................................................21 3.3.4 Egress Microblock .................................................................................................21 3.4 Transmit Processor Traffic Scheduler ................................................................................21 3.5 Transmit Processor Traffic Shaper .....................................................................................22 3.6 Transmit Processor Traffic Transmit...................................................................................22 4.0 Data and Tables......................................................................................................................22 4.1 Receive Processor..............................................................................................................22 4.1.1 Input Data ..............................................................................................................22 4.1.2 Output Data ...........................................................................................................26 4.2 Transmit Processor.............................................................................................................28 4.2.1 Input Data ..............................................................................................................28 4.2.2 Output Data ...........................................................................................................29 4.3 Connection, Routing, and Hash Tables ..............................................................................29 4.3.1 Rate Manager ........................................................................................................30 4.3.1.1 Port Table Entry .....................................................................................30 4.3.1.2 VC Table Entry.......................................................................................31 5.0 Project Configuration / Modifying the Example Design ........................................32 6.0 Testing Environment............................................................................................................32 7.0 Simulation Support (Scripts, etc.) ..................................................................................32 7.1 Simulation for the Receive Processor Project ....................................................................32 Application Note
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