Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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Digital Subscriber Line Access Multiplexer (DSLAM) Example Design Figure 12 shows how flow control packets are formatted. These packets are then prepended with the custom DSLAM header by the DSL Aggregator. The flow control packets with the prepended DSLAM headers are the input to the Receive Processor. Figure 12. Receive Processor Input - Flow Control Packet with DSLAM Header Flow Control Flow Control Valid 1 bit Flow Control Message 2 bits Flow ID 13 bits Padding 46 bytes DSLAM (input to Processor A) DSLAM Header 4 bytes Flow Control 48 bytes Packet Type 1 bit 0=flow control Unused 18 bits Physical Port Number 11 bits (0-2047) Physical Port Type 2 bits 1=ATM Note: Flow Control Format Flow Control Valid: 0=flow control invalid, 1-flow control valid Flow Control Message: 1=go, 1=no go Flow ID: 0-8191 A9555-01 4.1.2 Output Data Data packets and flow control packets are output from the Receive Processor. This output is formatted so that the packets may be received by an IXB3208 chip and forwarded on to the Transmit Processor. Data and flow control packets are prepended with an “inter-IXP” header containing packet classification data for use by the Transmit Processor. Then the packets, with their prepended inter-IXP header are segmented per IXB3208 requirements. A special header is prepended to each of these segments for consumption by the IXB3208. 26 Application Note
Digital Subscriber Line Access Multiplexer (DSLAM) Example Design Figure 13 shows how PDUs and flow control packets output from the Receive Processor to the IXB3208 are formatted. These PDUs and flow control packets are prepended with an inter-IXP header (containing classification information for traffic management), segmented, and then prepended with IXB3208 headers. (IXB3208 headers follow a standard format as specified in the IXB3208 documentation.) The input to the Transmit Processor is the same data with the IXB3208 headers stripped off by the IXB3208. Figure 13. Receive Processor Output to IXB3208 PDU or Flow Control Reassembled/modified PDU or Flow Control multiple of 48 bytes Classification Inter-IXP Header Reassembled/modified PDU or Flow Control SAR Sub-Layer (output from Processor A) Intel ® IXB3208 Header Payload 64 bytes Intel IXB3208 Header Payload 64 bytes Intel IXB3208 Header Payload 64 bytes A9556-01 Figure 14 shows the format of the Inter-IXP header, which is used to communicate packet classification data from the Receive Processor to the Transmit Processor. Figure 14. Inter-IXP Header Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Last Byte C A M Type CLP Priority Time Last Quadword in Packet in Packet 0 Source VC or Vport Destination VC or Multicast Group 1 Legend C A M CLP Type Priority Time Last Quadword in Packet Last Byte in Packet Source VC or Vport Destination VC or Multicast Group Control Indicator 0 = command packet 1 = data packet ATM Indicator 0 = unicast packet is not ATM 1 = unicast packet is ATM Multicast Indicator 0 = unicast packet 1 = multicast packet Cell Loss Priority Indicator Connection Type 1 = UBR 2 = VBR 4 = CBR The UBR Priority Time IXP1200 A spent on the packet in 1 microsec increments. The quadword offset from the start of the packet to the last quadword of data for the packet The last byte in packet is the number of valid bytes in the last quadword 1. These appear to be unique numbers per IP address. Application Note 27
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Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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