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Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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<strong>Digital</strong> <strong>Subscriber</strong> <strong>Line</strong> <strong>Access</strong> <strong>Multiplexer</strong> (<strong>DSLAM</strong>) <strong>Example</strong> <strong>Design</strong><br />

// Description:move mpacket to packet buffer and<br />

// update packet buffer address for next thread<br />

//<br />

// Outputs:<br />

// Now a global : out_exceptionif re-assembly failed, exception will be > 0<br />

//<br />

// Inputs/Outputs:<br />

// Now a global : rec_state mpacket status information<br />

// Now a global : packet_buf_addr sdram packet buffer address<br />

// Now a global : buffer_allocation_vector vector variable to keep track of<br />

which threads have a current buffer popped.<br />

//<br />

// Input:<br />

// my_mb this thread’s mailbox address for updated segment address<br />

// next_mb next thread’s mailbox address for updated segment address<br />

// next_tid next thread’s id for signaling<br />

// rec_req canned receive request for IX Bus<br />

// rfifo_addressrfifo address this thread will use<br />

//<br />

3.3.3 Transform Microblocks<br />

No transformations are done in the receive microblock group in the Transmit Processor.<br />

3.3.4 Egress Microblock<br />

One egress microblock is available for the receive microblock group in the Transmit Processor:<br />

• <strong>DSLAM</strong>_CopyEnqueue (enqueue to the traffic management system)<br />

The following function header describes the egress microblock. This function is contained in the<br />

files $Gen_<strong>DSLAM</strong>\hyannis\workbench_projects\dslam_proc_b_uC\main0.c and<br />

$Gen_<strong>DSLAM</strong>\hyannis\workbench_projects\dslam_proc_b_uC\main1.c.<br />

// ************************************************************************<br />

// <strong>DSLAM</strong>_CopyEnqueue<br />

// ************************************************************************<br />

//<br />

// Description:<br />

// Get the inter ixp header either from memory, or from the rfifo if sop.<br />

// Determine if the packet is flow control or data.<br />

// If flow control, then update the flow control table and set the bit<br />

// according the vc either on or off.<br />

// If data, then create a message for the tm41_receive code, and send it.<br />

//<br />

// Inputs:<br />

// Now a global : rec_statempacket status information<br />

// rfifo_addressrfifo address this thread will use<br />

// Now a global : packet_buf_addr packet buffer address<br />

//<br />

3.4 Transmit Processor Traffic Scheduler<br />

The TM4.1_Scheduler function schedules cells for transmit based on traffic contract associated<br />

with a VC. It schedules shaped VCs that have strict time constraints and unshaped VCs scheduled<br />

using the residual bandwidth after processing shaped VCs. The TM4.1_Scheduler function looks<br />

for work either from the message queue originating from the TM4.1_Receive function or a<br />

message queue originating from TM4.1_Shaper function. The schedule (comprising the VP/VC to<br />

be processed) for the shaped and unshaped VC is stored in a calendar queue.<br />

Application Note 21

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