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Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

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<strong>Digital</strong> <strong>Subscriber</strong> <strong>Line</strong> <strong>Access</strong> <strong>Multiplexer</strong> (<strong>DSLAM</strong>) <strong>Example</strong> <strong>Design</strong><br />

3.2 Receive Processor Transmit Microblock Group<br />

Figure 8 shows the data flow for the transmit microblock group in the Receive Processor. This flow<br />

also represents the dispatch loop used to control the microblock group.<br />

Figure 8. Receive Processor Transmit Microblock Group<br />

Conditionally compiled depending upon<br />

Intel ® IXB3208 Network Processor<br />

Support Definition<br />

<strong>DSLAM</strong>_Initialize_<br />

Transmit_uBlock_<br />

Group_A_IXB3208<br />

<strong>DSLAM</strong>_Initialize_<br />

Transmit_uBlock_<br />

Group_A<br />

Conditionally<br />

compiled<br />

depending upon<br />

Intel IXB3208<br />

Network Processor<br />

Support Definition<br />

<strong>DSLAM</strong>_Copy_<br />

Enqueue_IXB3208<br />

outgoing_pkt<br />

with prepended<br />

Intel IXB3208<br />

Header<br />

constants and sequences<br />

and<br />

Initializations of<br />

<strong>DSLAM</strong>_<br />

Dequeue<br />

Initializations<br />

sequences<br />

constants<br />

pdu<br />

of<br />

pdu<br />

<strong>DSLAM</strong>_Copy_<br />

Enqueue<br />

TFIFO<br />

outgoing_pkt<br />

pkt<br />

queue<br />

outgoing_pkt<br />

A9552-01<br />

Application Note 19

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