Digital Subscriber Line Access Multiplexer (DSLAM) Example Design

Digital Subscriber Line Access Multiplexer (DSLAM) Example Design
On the data path in the Transmit Processor, 64-byte segmented chunks of data are received from
the IXB3208. They are reassembled into full PDUs, which already include padding and an AAL5
trailer. The PDUs are then scheduled and shaped according to their contract, segmented and then
transmitted back out to the DSLAM aggregator.
2.1 Software Partitioning
Figure 2 shows how the design is partitioned between IXP1200 microengines in the Receive
Processor. There are four dedicated microengines receiving incoming DSLAM traffic, one
microengine transmitting to the IXB3208, and one spare microengine (not shown).
One ATM port, shown on the left side of the diagram supplies DSLAM cells to the receiving
microengines. They are assembled into PDUs or flow control packets, validation, IP lookups, and
header transformations are performed, and the resulting PDUs or flow control packets are queued
to the transmitting microengine. The transmitting microengine then segments the frames into 64-
byte chunks and transmits them to the IXB3208.
Figure 2. Receive Processor System Partitioning
Microengine
0
RFIFO
Microengine
1
Microengine
2
SDRAM
Buffers
Microengine
5
4 Transmitting threads
running on 1 Microengine
TFIFO
Microengine
3
16 Receiving threads
running on 4 Microengines
A9548-01
8 Application Note