PC Architecture. A book by Michael B. Karbo

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ISA was an improvement to IBM’s original XT bus (which was only 8 bits wide) IBM used the protected name ”AT Bus”, but in everyday conversation it was called the ISA bus. The ISA bus was 16 bits wide, and ran at a maximum clock frequency of 8 MHz. The bus has a theoretical bandwidth of about 8 MB per second. However in practise it never exceeds about 1-2 MB/sec. – partly because it takes 2-3 of the processor’s clock pulses to move a packet (16 bits) of data. Fig. 166. The ISA bus is not used much today, but it had enormous significance in the years up until the middle of the 1990’s. The ISA bus had two ”faces” in the old PC architecture: ● An internal ISA bus, which the simple ports (the keyboard, floppy disk and serial/parallel ports) were connected to. ● An external expansion bus, to which 16-bit ISA adapters could be connected. Sluggish performance One of the reasons the ISA bus was slow was that it only had 16 data channels. The 486 processor, once it was introduced, worked with 32 bits each clock pulse. When it sent data to the ISA bus, these 32-bit packets (dwords or doublewords) had to be split into two 16-bit packets (two words), which were sent one at a time, and this slowed down the flow of data. Bus Time per packet ISA 375 ns 16 bits PCI 30 ns Amount of data per packet 32 bits Fig. 167. The PCI bus was a huge step forward. The ISA bus was not ”intelligent” either, since it was in principle the CPU which controlled all the work the bus was doing. This meant the CPU could only begin a new task when the transfer was complete. You may perhaps have experienced yourself, that when your PC works with the floppy disk drive – the rest of the PC virtually grinds to a halt. That’s the ISA bus’s fault, and it therefore only happens on older PC’s. These small delays are called wait states. If an ISA adapter cannot keep up with the data it is receiving, it sends wait states to the CPU. These are signals to the CPU telling it to do nothing. A wait state is a wasted clock pulse – the CPU skips over a clock pulse, without doing anything. Thus a slow ISA adapter could choke any PC. Another problem was that the ISA bus often played up when you were installing an expansion card (e.g. a sound card). Many of the problems were associated with the handling of IRQ’s and DMA channels (I will explain these terms later), which often had to be done ”by hand” with the old ISA bus. Every device takes up one particular IRQ, and possibly a DMA channel, and conflicts often arose with other devices. It was a big relief when Intel, in the late 1990’s, finally dropped the ISA bus and replaced it with the smart USB bus.
Fig. 168. ISA based Sound Blaster sound card. The MCA, EISA and VL buses The ISA bus was too slow, and the solution was to develop new standards for I/O devices. In 1987-88, two new I/O buses were put forward. First, IBM brought out their technologically advanced MCA bus. But since it was patented, a number of other companies pooled together to create the equivalent EISA bus. But neither MCA or EISA had a big impact on the clone market. We were stuck with the ISA bus up until 1993, when the VL bus finally became reasonably widespread. It was a genuine local bus, which means it worked synchronously with the system bus. The VL bus was very primitive; it was really just an extension of the system bus. The VL bus never managed to have a big impact, because almost at the same time, the robust and efficient PCI bus broke through. The various I/O buses are summarised below: Bus Description PC-XT from 1981 ISA (PC-AT) from 1984 MCA from 1987 EISA From 1988 VESA Local Bus from 1993 PCI from 1993 USB and Firewire, from 1998 PCI Express from 2004 Synchronous 8-bit bus which followed the CPU clock frequency of 4.77 or 6 MHz. Band width: 4-6 MB/sec. Simple, cheap I/O bus. Synchronous with the CPU. Band width: 8 MB/sec. Advanced I/O bus from IBM (patented). Asynchronous, 32-bit, at 10 MHz. Band width: 40 MB/sec. Advanced I/O bus (non-IBM), used especially in network servers. Asynchronous, 32-bit, at 8.33 MHz. Band width: 32 MB/sec. Simple, high-speed I/O bus. 32-bit, synchronised with the CPU’s clock frequency: 33, 40, 50 MHz. Band width: up to 160 MB/sec. Advanced, general, high-speed I/O bus. 32-bit, asynchronous, at 33 MHz. Band width: 133 MB/sec. Serial buses for external equipment. A serial bus for I/O cards with very high speed. Replaces PCI and AGP.
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PC Architecture - a book by Michael
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● Next chapter. ● Previous chap
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Copyright Michael Karbo , Denmark,
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IBM-compatible PCs, and as the year
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8 bit 8080 Small CP/M based home co
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In the winter of 1939 Atanasoff was
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Copyright Michael Karbo and ELI Aps
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Fig. 12. Cray supercomputer, 1976.
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Internal devices External devices M
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Fig. 21. Underneath the hard disk y
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Fig. 24. The motherboard is the hub
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Fig. 27. Here you can see three (wh
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Fig. 31. At the bottom left, you ca
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● Higher clock frequencies (which
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Which CPU? Fig. 35. The underside o
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Fig. 38. A CPU is shown here withou
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Fig. 39. If you are not sure which
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Fig. 44. The two chips which make u
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Sound facilities in a chipset canno
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● Other network, screen and sound
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Fig. 54. The CPU’s working speed
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Less power consumption The types of
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1993 Pentium 0.8/0.5/0.35 microns 1
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Fig. 67. The latest generations of
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Fig. 68. Cache RAM is much faster t
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AMD Athlon 64 64 bits 2200 MHz 17,6
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Fig. 78. The WCPUID program reports
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As the years have passed, changes h
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The pipeline is like a reverse asse
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Motorola G4 4 500 MHz Motorola G4e
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Fig. 91. In the Pentium 4, the inst
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Fig. 92. Re-writing numbers in floa
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will become. ● Improvements to th
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point numbers with just one instruc
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The first PC’s were 16-bit machin
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Page 85 and 86: Fig. 105. L2 cache running at half
Page 87 and 88: Fig. 108. Extreme CPU cooling using
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Page 91 and 92: Figur 112. The LGA 775 socket for P
Page 93 and 94: Figur 114. In the Athlon 64 the mem
Page 95 and 96: Figur 116. There are scores of diff
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Page 99 and 100: Fig. 119. With this architecture, t
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Page 107 and 108: Module or chip size All RAM modules
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Page 111 and 112: In the beginning the problem with D
Page 113 and 114: However, RAM also has to match the
Page 115 and 116: Modern motherboards for desktop use
Page 117 and 118: The new architecture is used for bo
Page 119 and 120: Figur 148. Report from the freeware
Page 121 and 122: Fig. 150. In reality, the RAM needs
Page 123 and 124: Fig. 152. The data path to the vide
Page 125 and 126: Texture cache and RAMDAC Textures a
Page 127 and 128: opportunities for extension really
Page 129 and 130: Clock freq. 66 - 1066 MHz Typically
Page 131 and 132: Figur 162. The features in this mot
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Page 137 and 138: As a result of all this, the periph
Page 139 and 140: Fig. 174. Using the CMOS setup prog
Page 143 and 144: Figure 44. The two chips which make
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Page 155 and 156: here. Wafers and die size Another C
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Page 165 and 166: Xeon processors are incredibly expe
Page 167 and 168: You can no doubt see that it wouldn
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Page 173 and 174: Figure 90. The passage of instructi
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Page 177 and 178: FPU - the number cruncher Floating
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Figure 105. L2 cache running at hal
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As was mentioned earlier, the older
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Figur 112. The LGA 775 socket for P
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The Opteron is the most expensive a
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Figure 120. The bus system for an 8
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Figure 123. Setting the CPU voltage
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Figure 129. A 512 MB DDR RAM module
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DDR2-400 400 MHz DDR2 RAM DDR2-533
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Figure 137. The motherboard BIOS ca
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Of course you want to choose the be
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Under the Processes tab, you can se
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Figure 147. The architecture surrou
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Figure 149. The new chipset archite
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At the same time, the PCI system is
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Figure 156. The black PCI Express X
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Figure 157. The south bridge connec
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● The MCI, EISA and VL buses - fa
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Figure 164. The ATA interface works
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The ISA bus is thus the I/O bus whi
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MCA from 1987 Advanced I/O bus from
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Figure 172. The PCI bus is being re
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Figure 174. Using the CMOS setup pr
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Figure 178. The keyboard controller
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IRQ’s. It didn’t take much befo
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Memory-mapped I/O All devices, adap
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Figure 188. Here is the Audigy card
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Finally, I will look at the FireWir
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The super I/O controller is connect
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Figure 196. In the middle you see t
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Figure 200. The UART controller rep
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number of different SCSI standards.
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Figur 205. SCSI hard disks anno 200
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Figure 207. A USB-based trackball -
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USB has thus made the serial ports
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Figure 211. In the middle of the pi
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Figure 213. An SATA-hard disk (here
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from the disk. This magnetism will
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In the ”old days”, interfaces s
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Figure 220. This motherboard has an
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Figure 224. Jumper to change betwee
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Figure 228. An ATA-RAID controller
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The existing PATA system has a limi
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CMOS and Setup The startup program
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Figure 237. Standard CMOS Features
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Figure 239. Advanced Chipset Featur
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Figure 241. The system information
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have seen, in the ROM circuits on t
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To perform an upgrade you first dow
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DMA. Direct Memory Access. A system
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PC Architecture. A book by Michael B. Karbo

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