PC Architecture. A book by Michael B. Karbo

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Figure 246. Your motherboard manual is worth studying. 30. Glossary Fairly early on in the guide I started to explain a number of terms. I will now conclude with even more of the same. Most of these expressions have been used in the guide; here is a brief explanation of them. AMR. Audio Modem Riser. A standard for small expansion cards which are mounted on the motherboard and which provide connectors for the motherboard’s built-in sound and modem functions. Only used in very cheap PC configurations. BIOS. Basic Input Output System. Program code which provides simple control over a hardware device. Bus Master. A controller property, which allows a PCI device to take control over the PCI bus, so that data can be exchanged directly with RAM. CMOS. Complementary Metal-Oxide Semiconductor. Really a name for the process technology used, among other things, for CPU’s. There is a CMOS storage chip on the motherboard which contains a database of information about the motherboard and the other hardware devices. CSA. Communication Streaming Architecture. An Intel design, where the Gigabit LAN controller plugs directly into the north bridge.
DMA. Direct Memory Access. A system which allows an ISA device to move data directly to and from RAM. DOS. Disk Operating System. A 16-bit operating system from the time before Windows. Can still be installed on any PC. DRAM. Dynamic RAM. Storage cells which are used for standard RAM modules. Requires a constant refresh signal to remember the data. ECC. Error Correcting Code. A type of RAM which can correct internal errors which might occur during program execution. Is used for DRAM in servers and in the CPU’s internal cache. ECP. Enhanced Capabilities Port. One of the parallel port’s modes. Requires the use of a DMA channel. EIDE. Enhanced IDE interface for hard disks. Also called PATA for Parallel ATA. EPP. Enhanced Parallel Port. One of the parallel port’s faster modes. Also called ”Bi-directional”, since data can run both ways through the port. ESCD. Extended System Configuration Data. A list of the installed PCI devices. Included in the CMOS storage. File system. A system for organising data at the sector level on, for example, a hard disk. E.g. FAT32, NTFS. IDE. Integrated Drive Electronics. Hard disk interface. IrDA. Infrared Data Association. Standard for wireless data transfer over short distances using infrared light (like your TV remote control). Local bus. A bus (e.g. the system bus) which runs synchronously with the clock frequency in a connected device. LPC. Low Pin Count. An Intel standard which is used, among other things, for non ISA-based Super I/O chips, designed with relatively few pins. Mode. A state which an interface or a system can work in. Multitasking. When a system can work on several jobs at the same time. PCI. Peripheral Component Interconnect. The traditional motherboard’s standard I/O bus. PCI Express. New standard replacing PCI and AGP. PIO. Programmed I/O. Protocol for IDE/EIDE interfaces. POST. Power On Self Test. The part of the BIOS programs which tests the PC during startup. Protected mode. The 32-bit program state which replaced real mode. Real mode. A 16-bit state which programs were limited to working in in the first CPU’s. Registers. Tiny, lightning fast RAM stores, built deep into the CPU. RAID. Redundant Arrays of Inexpensive Disks. SATA. Serial ATA.
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PC Architecture - a book by Michael
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● Next chapter. ● Previous chap
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Copyright Michael Karbo , Denmark,
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IBM-compatible PCs, and as the year
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8 bit 8080 Small CP/M based home co
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In the winter of 1939 Atanasoff was
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Copyright Michael Karbo and ELI Aps
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Fig. 12. Cray supercomputer, 1976.
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Internal devices External devices M
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Fig. 21. Underneath the hard disk y
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Fig. 24. The motherboard is the hub
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Fig. 27. Here you can see three (wh
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Fig. 31. At the bottom left, you ca
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● Higher clock frequencies (which
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Which CPU? Fig. 35. The underside o
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Fig. 38. A CPU is shown here withou
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Fig. 39. If you are not sure which
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Fig. 44. The two chips which make u
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Sound facilities in a chipset canno
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● Other network, screen and sound
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Fig. 54. The CPU’s working speed
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Less power consumption The types of
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1993 Pentium 0.8/0.5/0.35 microns 1
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Fig. 67. The latest generations of
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Fig. 68. Cache RAM is much faster t
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AMD Athlon 64 64 bits 2200 MHz 17,6
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Fig. 78. The WCPUID program reports
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As the years have passed, changes h
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The pipeline is like a reverse asse
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Motorola G4 4 500 MHz Motorola G4e
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Fig. 91. In the Pentium 4, the inst
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Fig. 92. Re-writing numbers in floa
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will become. ● Improvements to th
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point numbers with just one instruc
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The first PC’s were 16-bit machin
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another in all later generations of
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Fig. 105. L2 cache running at half
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Fig. 108. Extreme CPU cooling using
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Figur 112. The LGA 775 socket for P
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Figur 114. In the Athlon 64 the mem
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Figur 116. There are scores of diff
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present, CPU’s and motherboards h
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Fig. 119. With this architecture, t
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Figur 124. A gigantic cooler with t
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Module or chip size All RAM modules
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Fig. 135. Older RAM modules. FPM RA
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In the beginning the problem with D
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However, RAM also has to match the
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Modern motherboards for desktop use
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The new architecture is used for bo
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Figur 148. Report from the freeware
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Fig. 150. In reality, the RAM needs
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Fig. 152. The data path to the vide
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Texture cache and RAMDAC Textures a
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opportunities for extension really
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Clock freq. 66 - 1066 MHz Typically
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Figur 162. The features in this mot
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Fig. 168. ISA based Sound Blaster s
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As a result of all this, the periph
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Fig. 174. Using the CMOS setup prog
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Figure 44. The two chips which make
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Figure 47. The chipset’s south br
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Figure 51. This PC has two sound ca
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You will most likely want to have t
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The trend is towards ever increasin
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A grand new world … We can expect
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here. Wafers and die size Another C
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Figure 69. A cache increases the CP
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Celeron (later gen.), Pentium III,
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Athlon 64 128 KB 512 KB Athlon 64 F
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Xeon processors are incredibly expe
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You can no doubt see that it wouldn
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Intel Pentium 4 (first generation)
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Figure 90. The passage of instructi
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AMD’s 32 bit Athlon line can bare
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FPU - the number cruncher Floating
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for 32-bit integers, and one for 80
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Figure 101. Two 486’s from two di
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Figure 105. L2 cache running at hal
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As was mentioned earlier, the older
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Figur 112. The LGA 775 socket for P
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The Opteron is the most expensive a
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Figure 120. The bus system for an 8
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Figure 123. Setting the CPU voltage
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Figure 129. A 512 MB DDR RAM module
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DDR2-400 400 MHz DDR2 RAM DDR2-533
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Figure 137. The motherboard BIOS ca
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Of course you want to choose the be
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Under the Processes tab, you can se
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Figure 147. The architecture surrou
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Figure 149. The new chipset archite
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At the same time, the PCI system is
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Figure 156. The black PCI Express X
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Figure 157. The south bridge connec
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● The MCI, EISA and VL buses - fa
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Figure 164. The ATA interface works
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The ISA bus is thus the I/O bus whi
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MCA from 1987 Advanced I/O bus from
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Figure 172. The PCI bus is being re
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Figure 174. Using the CMOS setup pr
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Figure 178. The keyboard controller
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IRQ’s. It didn’t take much befo
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Memory-mapped I/O All devices, adap
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Page 249 and 250: Figure 188. Here is the Audigy card
Page 251 and 252: Finally, I will look at the FireWir
Page 255 and 256: The super I/O controller is connect
Page 257 and 258: Figure 196. In the middle you see t
Page 259 and 260: Figure 200. The UART controller rep
Page 261 and 262: number of different SCSI standards.
Page 263 and 264: Figur 205. SCSI hard disks anno 200
Page 265 and 266: Figure 207. A USB-based trackball -
Page 267 and 268: USB has thus made the serial ports
Page 269 and 270: Figure 211. In the middle of the pi
Page 271 and 272: Figure 213. An SATA-hard disk (here
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Page 275 and 276: In the ”old days”, interfaces s
Page 277 and 278: Figure 220. This motherboard has an
Page 279 and 280: Figure 224. Jumper to change betwee
Page 281 and 282: Figure 228. An ATA-RAID controller
Page 283 and 284: The existing PATA system has a limi
Page 287 and 288: CMOS and Setup The startup program
Page 289 and 290: Figure 237. Standard CMOS Features
Page 291 and 292: Figure 239. Advanced Chipset Featur
Page 293 and 294: Figure 241. The system information
Page 295 and 296: have seen, in the ROM circuits on t
Page 297: To perform an upgrade you first dow
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