PC Architecture. A book by Michael B. Karbo

Athlon 64 128 KB 512 KB
Athlon 64 FX 128 KB 1024 KB
Pentium 4 (III, “Prescott”) 28 KB 1024 KB
Figure 76. The most common processors and their caches.
Latency
A very important aspect of all RAM – cache included – is latency. All RAM storage has a certain latency, which
means that a certain number of clock ticks (cycles) must pass between, for example, two reads. L1 cache has less
latency than L2; which is why it is so efficient.
When the cache is bypassed to read directly from RAM, the latency is many times greater. In Fig. 77 the number of
wasted clock ticks are shown for various CPU’s. Note that when the processor core has to fetch data from the actual
RAM (when both L1 and L2 have failed), it costs around 150 clock ticks. This situation is called stalling and needs to
be avoided.
Note that the Pentium 4 has a much smaller L1 cache than the Athlon XP, but it is significantly faster. It simply
takes fewer clock ticks (cycles) to fetch data:
Latency Pentium II Athlon Pentium 4
L1 cache: 3 cycles 3 cycles 2 cycles
L2 cache: 18 cycles 6 cycles 5 cycles
Figure 77. Latency leads to wasted clock ticks; the fewer there are of these, the faster the processor will appear to
be.
Intelligent ”data prefetch”
In CPU’s like the Pentium 4 and Athlon XP, a handful of support mechanisms are also used which work in parallel
with the cache. These include:
A hardware auto data prefetch unit, which attempts to guess which data should be read into the cache. This device
monitors the instructions being processed and predicts what data the next job will need.
Related to this is the Translation Look-aside Buffer, which is also a kind of cache. It contains information which
constantly supports the supply of data to the L1 cache, and this buffer is also being optimised in new processor
designs. Both systems contribute to improved exploitation of the limited bandwidth in the memory system.