PC Architecture. A book by Michael B. Karbo

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The new architecture is used for both Pentium 4 and Athlon processors, and in chipsets from Intel, VIA, and others. In reality, it doesn’t make a great deal of difference whether the chipset consists of hubs or bridges, so in the rest of the guide I will use both names indiscriminately. Figure 146. The MCH is the central part of the i875P chip set. The i875P chipset In 2003, Intel launched a chipset which work with the Pentium 4 and dual channel DDR RAM, each running at 200 MHz. This chip set became very popular, since it had a very good performance.
Figure 147. The architecture surrounding the Intel® 82875P Memory Controller Hub (MCH). Another new feature in this chip set is that a Gigabit Ethernet controller can have direct access to the MCH (the north bridge). Traditionally the LAN controller is connected to the <strong>PC</strong>I bus. But since a gigabit network controller may consume a great band width, it is better to plug it directly into north bridge. This new design is called Communication Streaming <strong>Architecture</strong> (CSA).
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PC Architecture - a book by Michael
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● Next chapter. ● Previous chap
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Copyright Michael Karbo , Denmark,
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IBM-compatible PCs, and as the year
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8 bit 8080 Small CP/M based home co
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In the winter of 1939 Atanasoff was
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Copyright Michael Karbo and ELI Aps
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Fig. 12. Cray supercomputer, 1976.
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Internal devices External devices M
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Fig. 21. Underneath the hard disk y
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Fig. 24. The motherboard is the hub
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Fig. 27. Here you can see three (wh
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Fig. 31. At the bottom left, you ca
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● Higher clock frequencies (which
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Which CPU? Fig. 35. The underside o
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Fig. 38. A CPU is shown here withou
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Fig. 39. If you are not sure which
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Fig. 44. The two chips which make u
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Sound facilities in a chipset canno
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● Other network, screen and sound
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Fig. 54. The CPU’s working speed
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Less power consumption The types of
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1993 Pentium 0.8/0.5/0.35 microns 1
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Fig. 67. The latest generations of
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Fig. 68. Cache RAM is much faster t
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AMD Athlon 64 64 bits 2200 MHz 17,6
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Fig. 78. The WCPUID program reports
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As the years have passed, changes h
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The pipeline is like a reverse asse
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Motorola G4 4 500 MHz Motorola G4e
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Fig. 91. In the Pentium 4, the inst
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Fig. 92. Re-writing numbers in floa
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will become. ● Improvements to th
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point numbers with just one instruc
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The first PC’s were 16-bit machin
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another in all later generations of
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Fig. 105. L2 cache running at half
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Fig. 108. Extreme CPU cooling using
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Figur 112. The LGA 775 socket for P
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Figur 114. In the Athlon 64 the mem
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Figur 116. There are scores of diff
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present, CPU’s and motherboards h
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Fig. 119. With this architecture, t
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Figur 124. A gigantic cooler with t
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Module or chip size All RAM modules
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Fig. 135. Older RAM modules. FPM RA
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In the beginning the problem with D
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However, RAM also has to match the
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Modern motherboards for desktop use
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The new architecture is used for bo
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Figur 148. Report from the freeware
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Fig. 150. In reality, the RAM needs
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Fig. 152. The data path to the vide
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Texture cache and RAMDAC Textures a
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opportunities for extension really
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Clock freq. 66 - 1066 MHz Typically
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Figur 162. The features in this mot
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Fig. 168. ISA based Sound Blaster s
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As a result of all this, the periph
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Fig. 174. Using the CMOS setup prog
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Figure 44. The two chips which make
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Figure 47. The chipset’s south br
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Figure 51. This PC has two sound ca
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You will most likely want to have t
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The trend is towards ever increasin
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A grand new world … We can expect
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here. Wafers and die size Another C
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Figure 69. A cache increases the CP
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Celeron (later gen.), Pentium III,
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Page 165 and 166: Xeon processors are incredibly expe
Page 167 and 168: You can no doubt see that it wouldn
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Page 171 and 172: Intel Pentium 4 (first generation)
Page 173 and 174: Figure 90. The passage of instructi
Page 175 and 176: AMD’s 32 bit Athlon line can bare
Page 177 and 178: FPU - the number cruncher Floating
Page 179 and 180: for 32-bit integers, and one for 80
Page 183 and 184: Figure 101. Two 486’s from two di
Page 185 and 186: Figure 105. L2 cache running at hal
Page 187 and 188: As was mentioned earlier, the older
Page 189 and 190: Figur 112. The LGA 775 socket for P
Page 191 and 192: The Opteron is the most expensive a
Page 197 and 198: Figure 120. The bus system for an 8
Page 199 and 200: Figure 123. Setting the CPU voltage
Page 203 and 204: Figure 129. A 512 MB DDR RAM module
Page 205 and 206: DDR2-400 400 MHz DDR2 RAM DDR2-533
Page 207 and 208: Figure 137. The motherboard BIOS ca
Page 209 and 210: Of course you want to choose the be
Page 211 and 212: Under the Processes tab, you can se
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Page 217 and 218: Figure 149. The new chipset archite
Page 221 and 222: At the same time, the PCI system is
Page 223 and 224: Figure 156. The black PCI Express X
Page 225 and 226: Figure 157. The south bridge connec
Page 227 and 228: ● The MCI, EISA and VL buses - fa
Page 229 and 230: Figure 164. The ATA interface works
Page 231 and 232: The ISA bus is thus the I/O bus whi
Page 233 and 234: MCA from 1987 Advanced I/O bus from
Page 235 and 236: Figure 172. The PCI bus is being re
Page 237 and 238: Figure 174. Using the CMOS setup pr
Page 241 and 242: Figure 178. The keyboard controller
Page 243 and 244: IRQ’s. It didn’t take much befo
Page 245 and 246: Memory-mapped I/O All devices, adap
Page 249 and 250: Figure 188. Here is the Audigy card
Page 251 and 252: Finally, I will look at the FireWir
Page 255 and 256: The super I/O controller is connect
Page 257 and 258: Figure 196. In the middle you see t
Page 259 and 260: Figure 200. The UART controller rep
Page 261 and 262: number of different SCSI standards.
Page 263 and 264: Figur 205. SCSI hard disks anno 200
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Figure 207. A USB-based trackball -
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USB has thus made the serial ports
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Figure 211. In the middle of the pi
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Figure 213. An SATA-hard disk (here
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from the disk. This magnetism will
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In the ”old days”, interfaces s
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Figure 220. This motherboard has an
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Figure 224. Jumper to change betwee
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Figure 228. An ATA-RAID controller
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The existing PATA system has a limi
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CMOS and Setup The startup program
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Figure 237. Standard CMOS Features
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Figure 239. Advanced Chipset Featur
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Figure 241. The system information
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have seen, in the ROM circuits on t
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To perform an upgrade you first dow
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DMA. Direct Memory Access. A system
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PC Architecture. A book by Michael B. Karbo

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