PC Architecture. A book by Michael B. Karbo

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These MP (Multiprocessor) machines are typically used as servers, but can also be used as powerful workstations, for example, to perform demanding 3D graphics and animation tasks. AMD has the Opteron processors, which are server-versions of the Athlon 64. Not all software can make use of the PC’s extra processors; the programs have to be designed to do so. For example, there are professional versions of Windows NT, 2000 and XP, which support the use of several processors in one PC. See also the discussion of Hyper Threading, which allows a Pentium 4 processor to appear as an MP system. Both Intel and AMD also works on dual-core processors. ● Next chapter. ● Previous chapter.
Copyright Michael Karbo and ELI Aps., Denmark, Europe. ● Next chapter. ● Previous chapter. Chapter 12. Data and instructions Now it’s time to look more closely at the work of the CPU. After all, what does it actually do? Instructions and data Our CPU processes instructions and data. It receives orders from the software. The CPU is fed a gentle stream of binary data via the RAM. These instructions can also be called program code. They include the commands which you constantly – via user programs – send to your PC using your keyboard and mouse. Commands to print, save, open, etc. Data is typically user data. Think about that email you are writing. The actual contents (the text, the letters) is user data. But when you and your software say “send”, your are sending program code (instructions) to the processor: Fig. 80. The instructions process the user data. Instructions and compatibility Instructions are binary code which the CPU can understand. Binary code (machine code) is the mechanism by which PC programs communicate with the processor. All processors, whether they are in PC’s or other types of computers, work with a particular instruction set. These instructions are the language that the CPU understands, and thus all programs have to communicate using these instructions. Here is a simplified example of some “machine code” – instructions written in the language the processor understands: proc near
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PC Architecture - a book by Michael
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● Next chapter. ● Previous chap
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Copyright Michael Karbo , Denmark,
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IBM-compatible PCs, and as the year
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8 bit 8080 Small CP/M based home co
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In the winter of 1939 Atanasoff was
Page 13 and 14: Copyright Michael Karbo and ELI Aps
Page 15 and 16: Fig. 12. Cray supercomputer, 1976.
Page 19 and 20: Internal devices External devices M
Page 21 and 22: Fig. 21. Underneath the hard disk y
Page 23 and 24: Fig. 24. The motherboard is the hub
Page 25 and 26: Fig. 27. Here you can see three (wh
Page 27 and 28: Fig. 31. At the bottom left, you ca
Page 29 and 30: ● Higher clock frequencies (which
Page 31 and 32: Which CPU? Fig. 35. The underside o
Page 33 and 34: Fig. 38. A CPU is shown here withou
Page 35 and 36: Fig. 39. If you are not sure which
Page 39 and 40: Fig. 44. The two chips which make u
Page 43 and 44: Sound facilities in a chipset canno
Page 45 and 46: ● Other network, screen and sound
Page 47 and 48: Fig. 54. The CPU’s working speed
Page 51 and 52: Less power consumption The types of
Page 53 and 54: 1993 Pentium 0.8/0.5/0.35 microns 1
Page 55 and 56: Fig. 67. The latest generations of
Page 57 and 58: Fig. 68. Cache RAM is much faster t
Page 61 and 62: AMD Athlon 64 64 bits 2200 MHz 17,6
Page 63: Fig. 78. The WCPUID program reports
Page 67 and 68: As the years have passed, changes h
Page 69 and 70: The pipeline is like a reverse asse
Page 71 and 72: Motorola G4 4 500 MHz Motorola G4e
Page 73 and 74: Fig. 91. In the Pentium 4, the inst
Page 75 and 76: Fig. 92. Re-writing numbers in floa
Page 77 and 78: will become. ● Improvements to th
Page 79 and 80: point numbers with just one instruc
Page 81 and 82: The first PC’s were 16-bit machin
Page 83 and 84: another in all later generations of
Page 85 and 86: Fig. 105. L2 cache running at half
Page 87 and 88: Fig. 108. Extreme CPU cooling using
Page 91 and 92: Figur 112. The LGA 775 socket for P
Page 93 and 94: Figur 114. In the Athlon 64 the mem
Page 95 and 96: Figur 116. There are scores of diff
Page 97 and 98: present, CPU’s and motherboards h
Page 99 and 100: Fig. 119. With this architecture, t
Page 103 and 104: Figur 124. A gigantic cooler with t
Page 107 and 108: Module or chip size All RAM modules
Page 109 and 110: Fig. 135. Older RAM modules. FPM RA
Page 111 and 112: In the beginning the problem with D
Page 113 and 114: However, RAM also has to match the
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Modern motherboards for desktop use
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The new architecture is used for bo
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Figur 148. Report from the freeware
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Fig. 150. In reality, the RAM needs
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Fig. 152. The data path to the vide
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Texture cache and RAMDAC Textures a
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opportunities for extension really
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Clock freq. 66 - 1066 MHz Typically
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Figur 162. The features in this mot
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Copyright Michael Karbo and ELI Aps
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Fig. 168. ISA based Sound Blaster s
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As a result of all this, the periph
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Fig. 174. Using the CMOS setup prog
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Figure 44. The two chips which make
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Figure 47. The chipset’s south br
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Figure 51. This PC has two sound ca
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You will most likely want to have t
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The trend is towards ever increasin
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A grand new world … We can expect
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here. Wafers and die size Another C
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Figure 69. A cache increases the CP
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Celeron (later gen.), Pentium III,
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Athlon 64 128 KB 512 KB Athlon 64 F
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Xeon processors are incredibly expe
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You can no doubt see that it wouldn
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Intel Pentium 4 (first generation)
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Figure 90. The passage of instructi
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AMD’s 32 bit Athlon line can bare
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FPU - the number cruncher Floating
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for 32-bit integers, and one for 80
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Figure 101. Two 486’s from two di
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Figure 105. L2 cache running at hal
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As was mentioned earlier, the older
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Figur 112. The LGA 775 socket for P
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The Opteron is the most expensive a
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Figure 120. The bus system for an 8
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Figure 123. Setting the CPU voltage
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Figure 129. A 512 MB DDR RAM module
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DDR2-400 400 MHz DDR2 RAM DDR2-533
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Figure 137. The motherboard BIOS ca
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Of course you want to choose the be
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Under the Processes tab, you can se
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Figure 147. The architecture surrou
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Figure 149. The new chipset archite
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At the same time, the PCI system is
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Figure 156. The black PCI Express X
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Figure 157. The south bridge connec
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● The MCI, EISA and VL buses - fa
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Figure 164. The ATA interface works
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The ISA bus is thus the I/O bus whi
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MCA from 1987 Advanced I/O bus from
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Figure 172. The PCI bus is being re
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Figure 174. Using the CMOS setup pr
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Figure 178. The keyboard controller
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IRQ’s. It didn’t take much befo
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Memory-mapped I/O All devices, adap
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Figure 188. Here is the Audigy card
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Finally, I will look at the FireWir
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The super I/O controller is connect
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Figure 196. In the middle you see t
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Figure 200. The UART controller rep
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number of different SCSI standards.
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Figur 205. SCSI hard disks anno 200
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Figure 207. A USB-based trackball -
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USB has thus made the serial ports
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Figure 211. In the middle of the pi
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Figure 213. An SATA-hard disk (here
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from the disk. This magnetism will
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In the ”old days”, interfaces s
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Figure 220. This motherboard has an
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Figure 224. Jumper to change betwee
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Figure 228. An ATA-RAID controller
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The existing PATA system has a limi
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CMOS and Setup The startup program
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Figure 237. Standard CMOS Features
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Figure 239. Advanced Chipset Featur
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Figure 241. The system information
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have seen, in the ROM circuits on t
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To perform an upgrade you first dow
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DMA. Direct Memory Access. A system
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PC Architecture. A book by Michael B. Karbo

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