PC Architecture. A book by Michael B. Karbo

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Copyright Michael Karbo and ELI Aps., Denmark, Europe. ● Next chapter. ● Previous chapter. Chapter 17. The CPU’s immediate surroundings In this part of this guide, we dug down into the inner workings of the CPU. We well let it rest in peace now, and concentrate on the processor’s immediate surroundings. That is, the RAM and the chipset – or more precisely, the north bridge. In the first section of the guide I introduced the chipset, including the north bridge (see, for example, Fig. 46 on page 19), which connects the CPU to the PC’s memory — the RAM. The pathway to RAM The most important data path on the motherboard runs between the CPU and the RAM. Data is constantly pumped back and forth between the two, and this bus therefore often comes under focus when new generations of CPU’s, chipset’s and motherboards are released. The RAM sends and receives data on a bus, and this work involves a clock frequency. This means that all RAM has a speed, just like a CPU does. Unfortunately RAM is much slower than the CPU, and the buses on the motherboard have to make allowance for this fact. The XT architecture In the original PC design (the IBM XT), the CPU, RAM and I/O devices (which we will come to later) were connected on one and the same bus, and everything ran synchronously (at a common speed). The CPU decided which clock frequency the other devices had to work at: Fig. 118. In the original PC architecture, there was only one bus with one speed. The problem with this system was that the three devices were “locked to each other”; they were forced to work at the lowest common clock frequency. It was a natural architecture in the first PC’s, where the speed was very slow. The first division of the bus In 1987, Compaq hit on the idea of separating the system bus from the I/O bus, so that the two buses could work at different clock frequencies. By letting the CPU and RAM work on their own bus, independent of the I/O devices, their speeds could be increased. In Fig. 119, the CPU and RAM are connected to a common bus, called the system bus, where in reality the CPU’s clock frequency determines the working speed. Thus the RAM has the same speed as the CPU; for example, 12, 16 or 25 MHz.
Fig. 119. With this architecture, the I/O bus is separate from the system bus (80386). The I/O devices (graphics card, hard disk, etc.) were separated from the system bus and placed on a separate low speed bus. This was because they couldn’t keep up with the clock frequencies of the new CPU versions. The connection between the two buses is managed by a controller, which functions as a “bridge” between the two paths. This was the forerunner of the multibus architecture which all motherboards use today. Clock doubling With the introduction of the 80486, the CPU clock frequency could be increased so much that the RAM could no longer keep up. Intel therefore began to use clock doubling in the 80486 processor. The RAM available at the time couldn’t keep up with the 66 MHz speed at which an 80486 could work. The solution was to give the CPU two working speeds. ● An external clock frequency ● An internal clock frequency Inside the processor, the clock frequency of the system bus is multiplied by a factor of 2, doubling the working speed. Fig. 120. The bus system for an 80486 processor. But this system places heavy demands on the RAM, because when the CPU internally processes twice as much data, it of course has to be “fed” more often. The problem is, that the RAM only works half as fast as the CPU. For precisely this reason, the 486 was given a built-in L1 cache, to reduce the imbalance between the slow RAM and the fast processor. The cache doesn’t improve the bandwidth (the RAM doesn’t work any faster), but it ensures greater efficiency in the transfer of data to the CPU, so that it gets the right data supplied at the right time.
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PC Architecture - a book by Michael
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● Next chapter. ● Previous chap
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Copyright Michael Karbo , Denmark,
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IBM-compatible PCs, and as the year
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8 bit 8080 Small CP/M based home co
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In the winter of 1939 Atanasoff was
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Copyright Michael Karbo and ELI Aps
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Fig. 12. Cray supercomputer, 1976.
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Internal devices External devices M
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Fig. 21. Underneath the hard disk y
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Fig. 24. The motherboard is the hub
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Fig. 27. Here you can see three (wh
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Fig. 31. At the bottom left, you ca
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● Higher clock frequencies (which
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Which CPU? Fig. 35. The underside o
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Fig. 38. A CPU is shown here withou
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Fig. 39. If you are not sure which
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Fig. 44. The two chips which make u
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Sound facilities in a chipset canno
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● Other network, screen and sound
Page 47 and 48: Fig. 54. The CPU’s working speed
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Page 51 and 52: Less power consumption The types of
Page 53 and 54: 1993 Pentium 0.8/0.5/0.35 microns 1
Page 55 and 56: Fig. 67. The latest generations of
Page 57 and 58: Fig. 68. Cache RAM is much faster t
Page 61 and 62: AMD Athlon 64 64 bits 2200 MHz 17,6
Page 63 and 64: Fig. 78. The WCPUID program reports
Page 67 and 68: As the years have passed, changes h
Page 69 and 70: The pipeline is like a reverse asse
Page 71 and 72: Motorola G4 4 500 MHz Motorola G4e
Page 73 and 74: Fig. 91. In the Pentium 4, the inst
Page 75 and 76: Fig. 92. Re-writing numbers in floa
Page 77 and 78: will become. ● Improvements to th
Page 79 and 80: point numbers with just one instruc
Page 81 and 82: The first PC’s were 16-bit machin
Page 83 and 84: another in all later generations of
Page 85 and 86: Fig. 105. L2 cache running at half
Page 87 and 88: Fig. 108. Extreme CPU cooling using
Page 91 and 92: Figur 112. The LGA 775 socket for P
Page 93 and 94: Figur 114. In the Athlon 64 the mem
Page 95 and 96: Figur 116. There are scores of diff
Page 97: present, CPU’s and motherboards h
Page 103 and 104: Figur 124. A gigantic cooler with t
Page 107 and 108: Module or chip size All RAM modules
Page 109 and 110: Fig. 135. Older RAM modules. FPM RA
Page 111 and 112: In the beginning the problem with D
Page 113 and 114: However, RAM also has to match the
Page 115 and 116: Modern motherboards for desktop use
Page 117 and 118: The new architecture is used for bo
Page 119 and 120: Figur 148. Report from the freeware
Page 121 and 122: Fig. 150. In reality, the RAM needs
Page 123 and 124: Fig. 152. The data path to the vide
Page 125 and 126: Texture cache and RAMDAC Textures a
Page 127 and 128: opportunities for extension really
Page 129 and 130: Clock freq. 66 - 1066 MHz Typically
Page 131 and 132: Figur 162. The features in this mot
Page 135 and 136: Fig. 168. ISA based Sound Blaster s
Page 137 and 138: As a result of all this, the periph
Page 139 and 140: Fig. 174. Using the CMOS setup prog
Page 143 and 144: Figure 44. The two chips which make
Page 145 and 146: Figure 47. The chipset’s south br
Page 147 and 148: Figure 51. This PC has two sound ca
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You will most likely want to have t
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The trend is towards ever increasin
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A grand new world … We can expect
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here. Wafers and die size Another C
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Figure 69. A cache increases the CP
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Celeron (later gen.), Pentium III,
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Athlon 64 128 KB 512 KB Athlon 64 F
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Xeon processors are incredibly expe
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You can no doubt see that it wouldn
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Intel Pentium 4 (first generation)
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Figure 90. The passage of instructi
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AMD’s 32 bit Athlon line can bare
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FPU - the number cruncher Floating
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for 32-bit integers, and one for 80
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Figure 101. Two 486’s from two di
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Figure 105. L2 cache running at hal
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As was mentioned earlier, the older
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Figur 112. The LGA 775 socket for P
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The Opteron is the most expensive a
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Figure 120. The bus system for an 8
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Figure 123. Setting the CPU voltage
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Figure 129. A 512 MB DDR RAM module
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DDR2-400 400 MHz DDR2 RAM DDR2-533
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Figure 137. The motherboard BIOS ca
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Of course you want to choose the be
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Under the Processes tab, you can se
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Figure 147. The architecture surrou
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Figure 149. The new chipset archite
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At the same time, the PCI system is
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Figure 156. The black PCI Express X
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Figure 157. The south bridge connec
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● The MCI, EISA and VL buses - fa
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Figure 164. The ATA interface works
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The ISA bus is thus the I/O bus whi
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MCA from 1987 Advanced I/O bus from
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Figure 172. The PCI bus is being re
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Figure 174. Using the CMOS setup pr
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Figure 178. The keyboard controller
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IRQ’s. It didn’t take much befo
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Memory-mapped I/O All devices, adap
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Figure 188. Here is the Audigy card
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Finally, I will look at the FireWir
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The super I/O controller is connect
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Figure 196. In the middle you see t
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Figure 200. The UART controller rep
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number of different SCSI standards.
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Figur 205. SCSI hard disks anno 200
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Figure 207. A USB-based trackball -
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USB has thus made the serial ports
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Figure 211. In the middle of the pi
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Figure 213. An SATA-hard disk (here
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from the disk. This magnetism will
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In the ”old days”, interfaces s
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Figure 220. This motherboard has an
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Figure 224. Jumper to change betwee
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Figure 228. An ATA-RAID controller
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The existing PATA system has a limi
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CMOS and Setup The startup program
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Figure 237. Standard CMOS Features
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Figure 239. Advanced Chipset Featur
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Figure 241. The system information
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have seen, in the ROM circuits on t
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To perform an upgrade you first dow
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DMA. Direct Memory Access. A system
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PC Architecture. A book by Michael B. Karbo

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