PC Architecture. A book by Michael B. Karbo

Figure 170. PCI bus adapter.
At the same time, the bus is compatible with the ISA bus to a certain extent, since PCI devices can
react to ISA bus signals, create the same IRQ’s etc. One consequence of this was that Sound Blaster
compatible sound cards could be developed, which was very important in the middle of the 1990’s. In
optimal conditions, the PCI bus sends one packet of data (32 bits) each clock pulse. The PCI bus
therefore has a maximum bandwidth of 132 MB per second, as shown below:
Clock
frequency:
33 MHz
Bus width: 32 bits
Bandwidth: 32 bits x 33,333,333 clock pulses/second =
4 bytes x 33,333,333 clock pulses/second =
132 MB per second
Figure 171. The maximum bandwidth of the PCI bus.
There is also a more powerful versions of the PCI standard, which provides greater bandwidth, but
most motherboards still use the original version. The PCI bus has a buffer which operates between the
CPU and the peripheral devices (a kind of cache RAM). This allows the CPU to deliver its data to the
buffer, and then perform other tasks. The bus looks after the rest of the delivery itself at its own pace.
Alternatively, PCI adapters can also deliver data to the buffer, whether or not the CPU has time to
process it. The data just stands in a queue and waits until there is room on the system bus, which then
relays it to the CPU.
As a result of all this, the peripheral PCI devices operate asynchronously – at their own pace – in
relation to the CPU. Thus the PCI bus (in contrast to the VL bus) is not a local bus from a technical
perspective.