Is Parallel Programming Hard, And, If So, What Can You Do About It?

Chapter 12Advanced Synchronization12.1 Avoiding LocksList the ways: RCU, non-blocking synchronization(notably simpler forms), memory barriers, deferredprocessing.@@@ Pull deferral stuff back to this section?12.2 Memory BarriersAuthor: David Howells and Paul McKenney.Causalityandsequencingaredeeplyintuitive, andhackers often tend to have a much stronger graspof these concepts than does the general population.These intuitions can be extremely powerfultools when writing, analyzing, and debugging bothsequential code and parallel code that makes useof standard mutual-exclusion mechanisms, such aslocking and RCU.Unfortunately, these intuitions break down completelyin face of code that makes direct use of explicitmemory barriers for data structures in sharedmemory (driver writers making use of MMIO registerscan place greater trust in their intuition, butmore on this @@@ later). The following sectionsshow exactly where this intuition breaks down, andthen puts forward a mental model of memory barriersthat can help you avoid these pitfalls.Section12.2.1givesabriefoverviewofmemoryorderingand memory barriers. Once this backgroundis in place, the next step is to get you to admit thatyour intuition has a problem. This painful task istaken up by Section 12.2.2, which shows an intuitivelycorrect code fragment that fails miserably onreal hardware, and by Section 12.2.3, which presentssome code demonstrating that scalar variables cantake on multiple values simultaneously. Once yourintuition has made it through the grieving process,Section 12.2.4 provides the basic rules that memorybarriers follow, rules that we will build upon.@@@ roadmap...12.2.1 Memory Ordering and MemoryBarriersBut why are memory barriers needed in the firstplace? Can’t CPUs keep track of ordering on theirown? Isn’t that why we have computers in the firstplace, to keep track of things?Many people do indeed expect their computers tokeep track of things, but many also insist that theykeep track of things quickly. One difficulty thatmodern computer-system vendors face is that themain memory cannot keep up with the CPU – modernCPUs can execute hundreds of instructions intime required to fetch a single variable from memory.CPUs therefore sport increasingly large caches,as shown in Figure 12.1. Variables that are heavilyused by a given CPU will tend to remain in thatCPU’s cache, allowing high-speed access to the correspondingdata.CPU 0 CPU 1CacheInterconnectMemoryCacheFigure 12.1: Modern Computer System CacheStructureUnfortunately, when a CPU accesses data thatis not yet in its cache will result in an expensive“cache miss”, requiring the data to be fetched frommain memory. Doubly unfortunately, running typ-