Is Parallel Programming Hard, And, If So, What Can You Do About It?

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238 APPENDIX D. READ-COPY UPDATE IMPLEMENTATIONS1 static int rcu_try_flip_waitzero(void)2 {3 int cpu;4 int lastidx = !(rcu_ctrlblk.completed & 0x1);5 int sum = 0;67 RCU_TRACE_ME(rcupreempt_trace_try_flip_z1);8 for_each_possible_cpu(cpu)9 sum += per_cpu(rcu_flipctr, cpu)[lastidx];10 if (sum != 0) {11 RCU_TRACE_ME(rcupreempt_trace_try_flip_ze1);12 return 0;13 }14 smp_mb();15 for_each_cpu_mask(cpu, rcu_cpu_online_map)16 per_cpu(rcu_mb_flag, cpu) = rcu_mb_needed;17 RCU_TRACE_ME(rcupreempt_trace_try_flip_z2);18 return 1;19 }Figure D.70: rcu try flip waitzero() Implementation1 static int rcu_try_flip_waitmb(void)2 {3 int cpu;45 RCU_TRACE_ME(rcupreempt_trace_try_flip_m1);6 for_each_cpu_mask(cpu, rcu_cpu_online_map)7 if (per_cpu(rcu_mb_flag, cpu) != rcu_mb_done) {8 RCU_TRACE_ME(rcupreempt_trace_try_flip_me1);9 return 0;10 }11 smp_mb();12 RCU_TRACE_ME(rcupreempt_trace_try_flip_m2);13 return 1;14 }Figure D.71: rcu try flip waitmb() Implementationline 7 checks to see if the current such CPU hasacknowledged the last counter flip. If not, line 9 tellsthe top-level grace-period state machine to remainin this state. Otherwise, if all online CPUs haveacknowledged, then line 11 does a memory barrier toensure that we don’t check for zeroes before the lastCPU acknowledges. This may seem dubious, butCPU designers have sometimes done strange things.Finally, line 13 tells the top-level grace-period statemachine to advance to the next state.The rcu_try_flip_waitzero() function, shownin Figure D.70, checks to see if all pre-existing RCUread-sidecriticalsectionshavecompleted, tellingthestate machine to advance if so. Lines 8 and 9 sumthe counters, and line 10 checks to see if the resultis zero, and, if not, line 12 tells the state machine tostay right where it is. Otherwise, line 14 executes amemory barrier to ensure that no CPU sees the subsequentcallforamemorybarrierbeforeithasexitedits last RCU read-side critical section. This possibilitymight seem remote, but again, CPU designershave done stranger things, and besides, this is anythingbut a fastpath. Lines 15 and 16 set all onlineCPUs’ rcu_mb_flag variables, and line 18 tells thestate machine to advance to the next state.The rcu_try_flip_waitmb() function, shown inFigure D.71, checks to see if all online CPUs haveexecuted the requested memory barrier, telling thestate machine to advance if so. Lines 6 and 7 checkeach online CPU to see if it has done the neededmemory barrier, and if not, line 9 tells the state machinenot to advance. Otherwise, if all CPUs haveexecuted a memory barrier, line 11 executes a memorybarrier to ensure that any RCU callback invocationfollows all of the memory barriers, and line 13tells the state machine to advance.1 static void __rcu_advance_callbacks(struct rcu_data *rdp)2 {3 int cpu;4 int i;5 int wlc = 0;67 if (rdp->completed != rcu_ctrlblk.completed) {8 if (rdp->waitlist[GP_STAGES - 1] != NULL) {9 *rdp->donetail = rdp->waitlist[GP_STAGES - 1];10 rdp->donetail = rdp->waittail[GP_STAGES - 1];11 RCU_TRACE_RDP(rcupreempt_trace_move2done, rdp);12 }13 for (i = GP_STAGES - 2; i >= 0; i--) {14 if (rdp->waitlist[i] != NULL) {15 rdp->waitlist[i + 1] = rdp->waitlist[i];16 rdp->waittail[i + 1] = rdp->waittail[i];17 wlc++;18 } else {19 rdp->waitlist[i + 1] = NULL;20 rdp->waittail[i + 1] =21 &rdp->waitlist[i + 1];22 }23 }24 if (rdp->nextlist != NULL) {25 rdp->waitlist[0] = rdp->nextlist;26 rdp->waittail[0] = rdp->nexttail;27 wlc++;28 rdp->nextlist = NULL;29 rdp->nexttail = &rdp->nextlist;30 RCU_TRACE_RDP(rcupreempt_trace_move2wait, rdp);31 } else {32 rdp->waitlist[0] = NULL;33 rdp->waittail[0] = &rdp->waitlist[0];34 }35 rdp->waitlistcount = wlc;36 rdp->completed = rcu_ctrlblk.completed;37 }38 cpu = raw_smp_processor_id();39 if (per_cpu(rcu_flip_flag, cpu) == rcu_flipped) {40 smp_mb();41 per_cpu(rcu_flip_flag, cpu) = rcu_flip_seen;42 smp_mb();43 }44 }rcu advance callbacks() Imple-Figure D.72:mentation
D.4. PREEMPTABLE RCU 2391 void __rcu_read_lock(void)2 {3 int idx;4 struct task_struct *t = current;5 int nesting;67 nesting = ACCESS_ONCE(t->rcu_read_lock_nesting);8 if (nesting != 0) {9 t->rcu_read_lock_nesting = nesting + 1;10 } else {11 unsigned long flags;1213 local_irq_save(flags);14 idx = ACCESS_ONCE(rcu_ctrlblk.completed) & 0x1;15 ACCESS_ONCE(__get_cpu_var(rcu_flipctr)[idx])++;16 ACCESS_ONCE(t->rcu_read_lock_nesting) = nesting + 1;17 ACCESS_ONCE(t->rcu_flipctr_idx) = idx;18 local_irq_restore(flags);19 }20 }Figure D.73: rcu read lock() ImplementationThe __rcu_advance_callbacks() function,shown in Figure D.72, advances callbacks andacknowledges the counter flip. Line 7 checks to seeif the global rcu_ctrlblk.completed counter hasadvanced since the last call by the current CPU tothis function. If not, callbacks need not be advanced(lines 8-37). Otherwise, lines 8 through 37 advancecallbacks through the lists (while maintaining acount of the number of non-empty lists in thewlc variable). In either case, lines 38 through 43acknowledge the counter flip if needed.Quick Quiz D.58: How is it possible for lines 38-43 of __rcu_advance_callbacks() to be executedwhen lines 7-37 have not? Won’t they both be executedjust after a counter flip, and never at anyother time?D.4.2.4 Read-Side PrimitivesThis section examines the rcu_read_lock() andrcu_read_unlock() primitives, followed by a discussionof how this implementation deals with thefact that these two primitives do not contain memorybarriers.rcu read lock() The implementation of rcu_read_lock() is as shown in Figure D.73. Line 7fetches this task’s RCU read-side critical-sectionnesting counter. If line 8 finds that this counter isnon-zero, then we are already protected by an outerrcu_read_lock(), in which case line 9 simply incrementsthis counter.However, if this is the outermost rcu_read_lock(), then more work is required. Lines 13 and 18suppressandrestoreirqstoensurethattheinterveningcode is neither preempted nor interrupted by ascheduling-clock interrupt (which runs the grace periodstatemachine).Line14fetchesthegrace-periodcounter, line 15 increments the current counter forthis CPU, line 16 increments the nesting counter,and line 17 records the old/new counter index sothat rcu_read_unlock() can decrement the correspondingcounter (but on whatever CPU it ends uprunning on).The ACCESS_ONCE() macros force the compiler toemit the accesses in order. Although this does notprevent the CPU from reordering the accesses fromthe viewpoint of other CPUs, it does ensure thatNMI and SMI handlers running on this CPU will seethese accesses in order. This is critically important:1. In absence of the ACCESS_ONCE() in the assignmentto idx, the compiler would be withinits rights to: (a) eliminate the local variableidx and (b) compile the increment on line 16as a fetch-increment-store sequence, doing separateaccesses to rcu_ctrlblk.completed forthe fetch and the store. If the value of rcu_ctrlblk.completed had changed in the meantime,this would corrupt the rcu_flipctr values.2. If the assignment to rcu_read_lock_nesting(line 17) were to be reordered to precede theincrement of rcu_flipctr (line 16), and if anNMI occurred between these two events, thenan rcu_read_lock() in that NMI’s handlerwould incorrectly conclude that it was alreadyunder the protection of rcu_read_lock().3. If the assignment to rcu_read_lock_nesting(line 17) were to be reordered to follow the assignmentto rcu_flipctr_idx (line 18), andif an NMI occurred between these two events,then an rcu_read_lock() in that NMI’s handlerwould clobber rcu_flipctr_idx, possiblycausing the matching rcu_read_unlock() todecrement the wrong counter. This in turncould result in premature ending of a grace period,indefinite extension of a grace period, oreven both.It is not clear that the ACCESS_ONCE on the assignmentto nesting (line 7) is required. It is alsounclear whether the smp_read_barrier_depends()(line 15) is needed: it was added to ensure thatchanges to index and value remain ordered.The reasons that irqs must be disabled fromline 13 through line 19 are as follows:1. Suppose one CPU loaded rcu_ctrlblk.completed (line 14), then a second CPU incrementedthis counter, and then the first CPU
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Is Parallel Programming Hard, And,
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Contents1 Introduction 11.1 Histori
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CONTENTSv6 Locking 676.1 Staying Al
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CONTENTSviiB Synchronization Primit
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CONTENTSixE.7.1 Introduction to Pre
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PrefaceThe purpose of this book is
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Chapter 1IntroductionParallel progr
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1.2. PARALLEL PROGRAMMING GOALS 3CP
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1.3. ALTERNATIVES TO PARALLEL PROGR
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1.4. WHAT MAKES PARALLEL PROGRAMMIN
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1.5. GUIDE TO THIS BOOK 9other hand
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Chapter 2Hardware and its HabitsMos
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2.1. OVERVIEW 13Therefore, as shown
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16 CHAPTER 2. HARDWARE AND ITS HABI
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18 CHAPTER 2. HARDWARE AND ITS HABI
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20 CHAPTER 3. TOOLS OF THE TRADE1 p
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22 CHAPTER 3. TOOLS OF THE TRADE1 p
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24 CHAPTER 3. TOOLS OF THE TRADE1.1
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26 CHAPTER 3. TOOLS OF THE TRADEQui
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28 CHAPTER 3. TOOLS OF THE TRADE
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30 CHAPTER 4. COUNTING1 atomic_t co
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32 CHAPTER 4. COUNTING4.2.3 Eventua
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34 CHAPTER 4. COUNTINGvanish when t
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36 CHAPTER 4. COUNTINGper-thread va
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38 CHAPTER 4. COUNTING1 unsigned lo
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42 CHAPTER 4. COUNTING1 #define THE
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46 CHAPTER 4. COUNTINGReadsAlgorith
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48 CHAPTER 5. PARTITIONING AND SYNC
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68 CHAPTER 6. LOCKING1 int delete(i
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70 CHAPTER 7. DATA OWNERSHIP
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72 CHAPTER 8. DEFERRED PROCESSINGfo
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76 CHAPTER 8. DEFERRED PROCESSING
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108 CHAPTER 8. DEFERRED PROCESSING
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110 CHAPTER 9. APPLYING RCU1 struct
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112 CHAPTER 9. APPLYING RCU
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114 CHAPTER 10. VALIDATION: DEBUGGI
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116 CHAPTER 11. DATA STRUCTURES
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118 CHAPTER 12. ADVANCED SYNCHRONIZ
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138 CHAPTER 13. EASE OF USEFigure 1
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140 CHAPTER 13. EASE OF USE
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142 CHAPTER 14. TIME MANAGEMENT
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144 CHAPTER 15. CONFLICTING VISIONS
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154 APPENDIX A. IMPORTANT QUESTIONS
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156 APPENDIX A. IMPORTANT QUESTIONS
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158 APPENDIX B. SYNCHRONIZATION PRI
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160 APPENDIX B. SYNCHRONIZATION PRI
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162 APPENDIX C. WHY MEMORY BARRIERS
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184 APPENDIX D. READ-COPY UPDATE IM
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186 APPENDIX D. READ-COPY UPDATE IM
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330 APPENDIX G. GLOSSARY(2) A physi
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332 APPENDIX G. GLOSSARYnear by. Th
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334 APPENDIX G. GLOSSARY
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336 BIBLIOGRAPHY[But97]USA, March 2
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338 BIBLIOGRAPHY[HMB06][Hol03][HP95
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340 BIBLIOGRAPHY[McK06] Paul E. McK
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342 BIBLIOGRAPHYtor. Software - Pra
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344 BIBLIOGRAPHY[UoC08][VGS08]Berke
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346 APPENDIX H. CREDITSH.4 Original
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