Is Parallel Programming Hard, And, If So, What Can You Do About It?

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180 APPENDIX C. WHY MEMORY BARRIERS?C.8 Are Memory Barriers Forever?Therehavebeenanumberofrecentsystemsthataresignificantly less aggressive about out-of-order executionin general and re-ordering memory referencesin particular. Will this trend continue to the pointwhere memory barriers are a thing of the past?The argument in favor would cite proposed massivelymulti-threaded hardware architectures, sothateachthreadwouldwaituntilmemorywasready,with tens, hundreds, or even thousands of otherthreads making progress in the meantime. In suchan architecture, there would be no need for memorybarriers, because a given thread would simply waitfor all outstanding operations to complete beforeproceeding to the next instruction. Because therewould be potentially thousands of other threads, theCPU would be completely utilized, so no CPU timewould be wasted.The argument against would cite the extremelylimited number of applications capable of scaling upto a thousand threads, as well as increasingly severerealtime requirements, which are in the tens ofmicroseconds for some applications. The realtimeresponserequirements are difficult enough to meetas is, and would be even more difficult to meet giventhe extremely low single-threaded throughput impliedby the massive multi-threaded scenarios.Another argument in favor would cite increasinglysophisticated latency-hiding hardware implementationtechniques that might well allow the CPUto provide the illusion of fully sequentially consistentexecution while still providing almost all of theperformance advantages of out-of-order execution.A counter-argument would cite the increasingly severepower-efficiency requirements presented bothby battery-operated devices and by environmentalresponsibility.Who is right? We have no clue, so are preparingto live with either scenario.C.9 Advice to Hardware DesignersThere are any number of things that hardware designerscan do to make the lives of software peopledifficult. Here is a list of a few such things that wehave encountered in the past, presented here in thehope that it might help prevent future such problems:1. I/O devices that ignore cache coherence.This charming misfeature can result in DMAsfrommemorymissingrecentchangestotheoutputbuffer, or, just as bad, cause input bufferstobeoverwrittenbythecontentsofCPUcachesjust after the DMA completes. To make yoursystem work in face of such misbehavior, youmust carefully flush the CPU caches of any locationinanyDMAbufferbeforepresentingthatbuffer to the I/O device. And even then, youneed to be very careful to avoid pointer bugs,as even a misplaced read to an input buffer canresult in corrupting the data input!2. External busses that fail to transmit cachecoherencedata.This is an even more painful variant of theabove problem, but causes groups of devices—and even memory itself—to fail to respect cachecoherence. It is my painful duty to inform youthatasembeddedsystemsmovetomulticorearchitectures,we will no doubt see a fair numberof such problems arise. Hopefully these problemswill clear up by the year 2015.3. Device interrupts that ignore cache coherence.This might sound innocent enough — after all,interrupts aren’t memory references, are they?But imagine a CPU with a split cache, one bankof which is extremely busy, therefore holdingontothelast cacheline oftheinput buffer. Ifthecorresponding I/O-complete interrupt reachesthis CPU, then that CPU’s memory referenceto the last cache line of the buffer could returnold data, again resulting in data corruption, butin a form that will be invisible in a later crashdump. By the time the system gets around todumping the offending input buffer, the DMAwill most likely have completed.4. Inter-processor interrupts (IPIs) that ignorecache coherence.This can be problematic if the IPI reaches itsdestination before all of the cache lines in thecorresponding message buffer have been committedto memory.5. Context switches that get ahead of cache coherence.If memory accesses can complete too wildly outoforder, thencontextswitchescanbequiteharrowing.If the task flits from one CPU to anotherbefore all the memory accesses visible tothesourceCPUmakeittothedestinationCPU,
C.9. ADVICE TO HARDWARE DESIGNERS 181then the task could easily see the correspondingvariables revert to prior values, which canfatally confuse most algorithms.6. Overly kind simulators and emulators.It is difficult to write simulators or emulatorsthat force memory re-ordering, so software thatruns just fine in these these environments canget a nasty surprise when it first runs on thereal hardware. Unfortunately, it is still the rulethat the hardware is more devious than are thesimulators and emulators, but we hope that thissituation changes.Again, we encourage hardware designers to avoidthese practices!
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Is Parallel Programming Hard, And,
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Contents1 Introduction 11.1 Histori
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CONTENTSv6 Locking 676.1 Staying Al
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CONTENTSviiB Synchronization Primit
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CONTENTSixE.7.1 Introduction to Pre
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PrefaceThe purpose of this book is
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Chapter 1IntroductionParallel progr
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1.2. PARALLEL PROGRAMMING GOALS 3CP
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1.3. ALTERNATIVES TO PARALLEL PROGR
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1.4. WHAT MAKES PARALLEL PROGRAMMIN
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1.5. GUIDE TO THIS BOOK 9other hand
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Chapter 2Hardware and its HabitsMos
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2.1. OVERVIEW 13Therefore, as shown
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16 CHAPTER 2. HARDWARE AND ITS HABI
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18 CHAPTER 2. HARDWARE AND ITS HABI
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20 CHAPTER 3. TOOLS OF THE TRADE1 p
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24 CHAPTER 3. TOOLS OF THE TRADE1.1
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26 CHAPTER 3. TOOLS OF THE TRADEQui
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28 CHAPTER 3. TOOLS OF THE TRADE
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30 CHAPTER 4. COUNTING1 atomic_t co
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32 CHAPTER 4. COUNTING4.2.3 Eventua
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34 CHAPTER 4. COUNTINGvanish when t
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36 CHAPTER 4. COUNTINGper-thread va
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38 CHAPTER 4. COUNTING1 unsigned lo
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42 CHAPTER 4. COUNTING1 #define THE
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46 CHAPTER 4. COUNTINGReadsAlgorith
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48 CHAPTER 5. PARTITIONING AND SYNC
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68 CHAPTER 6. LOCKING1 int delete(i
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70 CHAPTER 7. DATA OWNERSHIP
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72 CHAPTER 8. DEFERRED PROCESSINGfo
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76 CHAPTER 8. DEFERRED PROCESSING
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108 CHAPTER 8. DEFERRED PROCESSING
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110 CHAPTER 9. APPLYING RCU1 struct
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112 CHAPTER 9. APPLYING RCU
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114 CHAPTER 10. VALIDATION: DEBUGGI
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116 CHAPTER 11. DATA STRUCTURES
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118 CHAPTER 12. ADVANCED SYNCHRONIZ
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230 APPENDIX D. READ-COPY UPDATE IM
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244 APPENDIX E. FORMAL VERIFICATION
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272 APPENDIX F. ANSWERS TO QUICK QU
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330 APPENDIX G. GLOSSARY(2) A physi
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332 APPENDIX G. GLOSSARYnear by. Th
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334 APPENDIX G. GLOSSARY
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336 BIBLIOGRAPHY[But97]USA, March 2
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338 BIBLIOGRAPHY[HMB06][Hol03][HP95
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340 BIBLIOGRAPHY[McK06] Paul E. McK
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342 BIBLIOGRAPHYtor. Software - Pra
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344 BIBLIOGRAPHY[UoC08][VGS08]Berke
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346 APPENDIX H. CREDITSH.4 Original
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