Is Parallel Programming Hard, And, If So, What Can You Do About It?

126 CHAPTER 12. ADVANCED SYNCHRONIZATIONMemory barriers are such interventions. They imposea perceived partial ordering over the memoryoperations on either side of the barrier.Such enforcement is important because the CPUsand other devices in a system can use a variety oftricks to improve performance - including reordering,deferral and combination of memory operations;speculative loads; speculative branch prediction andvarious types of caching. Memory barriers are usedto override or suppress these tricks, allowing thecode to sanely control the interaction of multipleCPUs and/or devices.12.2.10.1 Explicit Memory BarriersMemory barriers come in four basic varieties:1. Write (or store) memory barriers,2. Data dependency barriers,3. Read (or load) memory barriers, and4. General memory barriers.Each variety is described below.Write Memory Barriers A write memory barriergivesaguaranteethatalltheSTOREoperationsspecified before the barrier will appear to happenbefore all the STORE operations specified after thebarrier with respect to the other components of thesystem.A write barrier is a partial ordering on stores only;it is not required to have any effect on loads.ACPUcanbeviewedascommittingasequenceofstore operations to the memory system as time progresses.All stores before a write barrier will occurin the sequence before all the stores after the writebarrier.† Note that write barriers should normally bepaired with read or data dependency barriers; seethe ”SMP barrier pairing” subsection.Data Dependency Barriers Adatadependencybarrier is a weaker form of read barrier. In the casewhere two loads are performed such that the seconddepends on the result of the first (eg: the first loadretrieves the address to which the second load willbe directed), a data dependency barrier would berequired to make sure that the target of the secondload is updated before the address obtained by thefirst load is accessed.A data dependency barrier is a partial ordering oninterdependent loads only; it is not required to haveany effect on stores, independent loads or overlappingloads.Asmentionedforwritememorybarriers, theotherCPUs in the system can be viewed as committingsequences of stores to the memory system that theCPU being considered can then perceive. A data dependencybarrier issued by the CPU under considerationguarantees that for any load preceding it, ifthatloadtouchesoneofasequenceofstoresfromanotherCPU, then by the time the barrier completes,the effects of all the stores prior to that touched bythe load will be perceptible to any loads issued afterthe data dependency barrier.See the ”Examples of memory barrier sequences”subsection for diagrams showing the ordering constraints.† Note that the first load really has to have a datadependency and not a control dependency. If theaddress for the second load is dependent on the firstload, but the dependency is through a conditionalrather than actually loading the address itself, thenit’s a control dependency and a full read barrier orbetter is required. See the ”Control dependencies”subsection for more information.† Note that data dependency barriers should normallybe paired with write barriers; see the ”SMPbarrier pairing” subsection.Read Memory Barriers A read barrier is a datadependency barrier plus a guarantee that all theLOAD operations specified before the barrier willappear to happen before all the LOAD operationsspecified after the barrier with respect to the othercomponents of the system.A read barrier is a partial ordering on loads only;it is not required to have any effect on stores.Read memory barriers imply data dependencybarriers, and so can substitute for them.† Note that read barriers should normally bepaired with write barriers; see the ”SMP barrierpairing” subsection.General Memory Barriers A general memorybarrier gives a guarantee that all the LOAD andSTORE operations specified before the barrier willappear to happen before all the LOAD and STOREoperations specified after the barrier with respect tothe other components of the system.A general memory barrier is a partial orderingover both loads and stores.General memory barriers imply both read andwrite memory barriers, and so can substitute for either.