Is Parallel Programming Hard, And, If So, What Can You Do About It?

Appendix GGlossaryAssociativity: The number of cache lines that canbe held simultaneously in a given cache, whenall of these cache lines hash identically in thatcache. A cache that could hold four cache linesfor each possible hash value would be termed a“four-way set-associative” cache, while a cachethat could hold only one cache line for eachpossible hash value would be termed a “directmapped”cache. A cache whose associativitywas equal to its capacity would be termeda “fully associative” cache. Fully associativecaches have the advantage of eliminateing associativitymisses, but, due to hardware limitations,fully associative caches are normallyquite limited in size. The associativity of thelarge caches found on modern microprocessorstypically range from two-way to eight-way.Associativity Miss: A cache miss incurred becausethe corresponding CPU has recently accessedmore data hashing to a given set of thecache than will fit in that set. Fully associativecaches are not subject to associativity misses(or, equivalently, in fully associative caches, associativityand capacity misses are identical).Atomic: Anoperationisconsidered“atomic”ifitisnot possible to observe any intermediate state.For example, on most CPUs, a store to a properlyaligned pointer is atomic, because otherCPUs will see either the old value or the newvalue, butareguaranteednottoseesomemixedvalue containing some pieces of the new and oldvalues.Cache: In modern computer systems, CPUs havecaches in which to hold frequently used data.These caches can be thought of as hardwarehashtableswithverysimplehashfunctions, butin which each hash bucket (termed a “set” byhardwaretypes)canholdonlyalimited numberof data items. The number of data items thatcan be held by each of a cache’s hash buckets istermed the cache’s “associativity”. These dataitems are normally called “cache lines”, whichcan be thought of a fixed-length blocks of datathat circulate among the CPUs and memory.Cache Coherence: A property of most modernSMPmachineswhereallCPUswillobserveasequenceof values for a given variable that is consistentwith at least one global order of valuesfor that variable. Cache coherence also guaranteesthat at the end of a group of stores to agiven variable, all CPUs will agree on the finalvalue for that variable. Note that cache coherenceapplies only to the series of values taken onby a single variable. In constrast, the memoryconsistency model for a given machine describesthe order in which loads and stores to groups ofvariables will appear to occur.Cache Coherence Protocol: A communicationsprotocol, normally implemented in hardware,that enforces memory consistency and ordering,preventing different CPUs from seeing inconsistentviews of data held in their caches.Cache Geometry: The size and associativity of acache is termed its geometry. Each cache maybe thought of as a two-dimensional array, withrows of cache lines (“sets”) that have the samehash value, and columns of cache lines (“ways”)in which every cache line has a different hashvalue. The associativity of a given cache is itsnumber of columns (hence the name “way” – atwo-way set-associative cache has two “ways”),and the size of the cache is its number of rowsmultiplied by its number of columns.Cache Line: (1) The unit of data that circulatesamong the CPUs and memory, usually a moderatepower of two in size. Typical cache-linesizes range from 16 to 256 bytes.