Is Parallel Programming Hard, And, If So, What Can You Do About It?

333handling more than one instruction. For example,if the conditions were exactly right, the IntelPentium Pro CPU from the mid-1990s couldexecute two (and sometimes three) instructionsper clock cycle. Thus, a 200MHz Pentium ProCPU could “retire”, or complete the executionof, up to 400 million instructions per second.Transactional Memory (TM): Shared-memorysynchronization scheme featuring “transactions”,each of which is an atomic sequence ofoperations that offers atomicity, consistency,isolation, but differ from classic transactionsin that they do not offer durability. Transactionalmemory may be implemented eitherin hardware (hardwre transactional memory,or HTM), in software (software transcationalmemory, or STM), or in a combination of hardwareand software (“unbounded” transactionalmemory, or UTM).Vector CPU: A CPU that can apply a single instructiontomultipleitemsofdataconcurrently.In the 1960s through the 1980s, only supercomputershad vector capabilities, but the adventof MMX in x86 CPUs and VMX in PowerPCCPUs brought vector processing to the masses.Write Miss: A cache miss incurred because thecorresponding CPU attempted to write to acache line that is read-only, most likely due toits being replicated in other CPUs’ caches.Write-Side Critical Section: A section of codeguarded by write-acquisition of some readerwritersynchronization mechanism. For example,if one set of critical sections are guardedby write-acquisition of a given global readerwriterlock, while a second set of critical sectionare guarded by read-acquisition of that samereader-writer lock, then the first set of criticalsections will be the write-side critical sectionsfor that lock. Only one thread may executein the write-side critical section at a time, andeven then only if there are no threads are executingconcurrently in any of the correspondingread-side critical sections.