Is Parallel Programming Hard, And, If So, What Can You Do About It?

12.2. MEMORY BARRIERS 129CPU 1 CPU 2a = 1;b = &a;x = b;y = *x;One way or another, the read barrier must alwaysbe present, even though it might be of a weakertype. 8Notethatthestoresbeforethewritebarrierwouldnormally be expected to match the loads after theread barrier or data dependency barrier, and viceversa:CPU 1a 1;b = 2;c 3;d = 4;CPU 2v cw = dx a;y = b;12.2.10.7 Examples of Memory BarrierPairingsFirstly, write barriers act as a partial orderings onstore operations. Consider the following sequence ofevents:STORE A = 1STORE B = 2STORE C = 3STORE D = 4STORE E = 5This sequence of events is committed to the memorycoherence system in an order that the rest ofthe system might perceive as the unordered set of{A=1,B=2,C=3} all occuring before the unorderedset of {D=4,E=5}, as shown in Figure 12.7.Secondly, data dependency barriers act as a partialorderings on data-dependent loads. Considerthe following sequence of events with initial values{B=7,X=9,Y=8,C=&Y}:8 By “weaker”, we mean ”makes fewer ordering guarantees”.A weaker barrier is usually also lower-overhead than isa stronger barrier.CPU 1 CPU 2a = 1;b = 2;c = &b;d = 4;LOAD XLOAD C (gets &B)LOAD *C (reads B)Without intervention, CPU 2 may perceive theevents on CPU 1 in some effectively random order,despite the write barrier issued by CPU 1:In the above example, CPU 2 perceives that B is7, despite the load of *C (which would be B) comingafter the the LOAD of C.If, however, a data dependency barrier were tobe placed between the load of C and the load of*C (i.e.: B) on CPU 2, again with initial values of{B=7,X=9,Y=8,C=&Y}:CPU 1 CPU 2a = 1;b = 2;c = &b;d = 4;LOAD XLOAD C (gets &B)LOAD *C (reads B)then ordering will be as intuitively expected, asshown in Figure 12.9.And thirdly, a read barrier acts as a partial orderon loads. Consider the following sequence of events,with initial values {A=0,B=9}:CPU 1 CPU 2a = 1;b = 2;LOAD BLOAD AWithout intervention, CPU 2 may then choose toperceive the events on CPU 1 in some effectivelyrandom order, despite the write barrier issued byCPU 1:If, however, a read barrier were to be placed betweenthe load of B and the load of A on CPU 2,again with initial values of {A=0,B=9}:CPU 1 CPU 2a = 1;b = 2;LOAD BLOAD A