Is Parallel Programming Hard, And, If So, What Can You Do About It?

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308 APPENDIX F. ANSWERS TO QUICK QUIZZESAnswer:The code assumes that as soon as a given CPU stopsseeing its own value, it will immediately see thefinal agreed-upon value. On real hardware, someof the CPUs might well see several intermediateresults before converging on the final value.Quick Quiz 12.4:How could CPUs possibly have different views ofthe value of a single variable at the same time?Answer:Many CPUs have write buffers that record thevalues of recent writes, which are applied once thecorresponding cache line makes its way to the CPU.Therefore, it is quite possible for each CPU to seea different value for a given variable at a singlepoint in time — and for main memory to hold yetanother value. One of the reasons that memorybarriers were invented was to allow software to dealgracefully with situations like this one.Quick Quiz 12.5:Why do CPUs 2 and 3 come to agreement soquickly, when it takes so long for CPUs 1 and 4 tocome to the party?Answer:CPUs 2 and 3 are a pair of hardware threads on thesame core, sharing the same cache hierarchy, andtherefore have very low communications latencies.This is a NUMA, or, more accurately, a NUCAeffect.This leads to the question of why CPUs 2 and 3ever disagree at all. One possible reason is that theyeach might have a small amount of private cache inaddition to a larger shared cache. Another possiblereason is instruction reordering, given the short 10-nanosecond duration of the disagreement and thetotal lack of memory barriers in the code fragment.Quick Quiz 12.6:But if the memory barriers do not unconditionallyforce ordering, how the heck can a device driverreliably execute sequences of loads and stores toMMIO registers???Answer:MMIO registers are special cases: because theyappear in uncached regions of physical memory.Memory barriers do unconditionally force orderingof loads and stores to uncached memory. SeeSection @@@ for more information on memorybarriers and MMIO regions.Quick Quiz 12.7:How could the assertion b==2 on page 122 possiblyfail?Answer:If the CPU is not required to see all of its loads andstores in order, then the b=1+a might well see anold version of the variable “a”.This is why it is so very important that each CPUor thread see all of its own loads and stores in programorder.Quick Quiz 12.8:How could the code on page 122 possibly leakmemory?Answer:Only the first execution of the critical section shouldsee p==NULL. However, if there is no global orderingof critical sections for mylock, then how can you saythat a particular one was first? If several differentexecutions of that critical section thought that theywere first, they would all see p==NULL, and theywould all allocate memory. All but one of thoseallocations would be leaked.This is why it is so very important that all thecritical sections for a given exclusive lock appear toexecute in some well-defined order.Quick Quiz 12.9:How could the code on page 122 possibly countbackwards?Answer:Suppose that the counter started out with thevalue zero, and that three executions of the criticalsection had therefore brought its value to three. Ifthe fourth execution of the critical section is notconstrained to see the most recent store to thisvariable, it might well see the original value of zero,and therefore set the counter to one, which wouldbe going backwards.This is why it is so very important that loads froma given variable in a given critical section see the laststore from the last prior critical section to store tothat variable.
F.10. CHAPTER 13: EASE OF USE 309Quick Quiz 12.10:What effect does the following sequence have on theorder of stores to variables “a” and “b”?a = 1;b = 1;Answer:Absolutely none. This barrier would ensure thatthe assignments to “a” and “b” happened beforeany subsequent assignments, but it does nothing toenforce any order of assignments to “a” and “b”themselves.Quick Quiz 12.11:What sequence of LOCK-UNLOCK operationswould act as a full memory barrier?Answer:A series of two back-to-back LOCK-UNLOCKoperations, or, somewhat less conventionally,an UNLOCK operations followed by a LOCKoperation.Quick Quiz 12.12:What (if any) CPUs have memory-barrier instructionsfrom which these semi-permiable lockingprimitives might be constructed?Answer:Itanium is one example. The identification of anyothers is left as an exercise for the reader.Quick Quiz 12.13:Given that operations grouped in curly bracesare executed concurrently, which of the rows ofTable 12.2 are legitimate reorderings of the assignmentsto variables “A” through “F” and theLOCK/UNLOCK operations? (The order in thecode is A, B, LOCK, C, D, UNLOCK, E, F.) Whyor why not?Answer:1. Legitimate, executed in order.2. Legitimate, the lock acquisition was executedconcurrently with the last assignment precedingthe critical section.3. Illegitimate, the assignment to “F” must followthe LOCK operation.4. Illegitimate, the LOCK must complete beforeany operation in the critical section. However,the UNLOCK may legitimately be executedconcurrently with subsequent operations.5. Legitimate, the assignment to “A” precedes theUNLOCK, as required, and all other operationsare in order.6. Illegitimate, the assignment to “C” must followthe LOCK.7. Illegitimate, the assignment to “D” must precedethe UNLOCK.8. Legitimate, all assignments are ordered with respectto the LOCK and UNLOCK operations.9. Illegitimate, the assignment to “A” must precedethe UNLOCK.Quick Quiz 12.14:What are the constraints for Table 12.2?Answer:They are as follows:1. LOCK M must precede B, C, and D.2. UNLOCK M must follow A, B, and C.3. LOCK Q must precede F, G, and H.4. UNLOCK Q must follow E, F, and G.F.10 Chapter 13: Ease of UseQuick Quiz 13.1:Can a similar algorithm be used when deletingelements?Answer:Yes. However, since each thread must hold the locksof three consecutive elements to delete the middleone, if there are N threads, there must be 2N + 1elements (rather than just N + 1 in order to avoiddeadlock.Quick Quiz 13.2:
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Is Parallel Programming Hard, And,
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Contents1 Introduction 11.1 Histori
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CONTENTSv6 Locking 676.1 Staying Al
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CONTENTSviiB Synchronization Primit
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CONTENTSixE.7.1 Introduction to Pre
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PrefaceThe purpose of this book is
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Chapter 1IntroductionParallel progr
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1.2. PARALLEL PROGRAMMING GOALS 3CP
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1.3. ALTERNATIVES TO PARALLEL PROGR
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1.4. WHAT MAKES PARALLEL PROGRAMMIN
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1.5. GUIDE TO THIS BOOK 9other hand
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Chapter 2Hardware and its HabitsMos
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2.1. OVERVIEW 13Therefore, as shown
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16 CHAPTER 2. HARDWARE AND ITS HABI
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18 CHAPTER 2. HARDWARE AND ITS HABI
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20 CHAPTER 3. TOOLS OF THE TRADE1 p
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22 CHAPTER 3. TOOLS OF THE TRADE1 p
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24 CHAPTER 3. TOOLS OF THE TRADE1.1
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28 CHAPTER 3. TOOLS OF THE TRADE
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30 CHAPTER 4. COUNTING1 atomic_t co
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32 CHAPTER 4. COUNTING4.2.3 Eventua
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34 CHAPTER 4. COUNTINGvanish when t
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36 CHAPTER 4. COUNTINGper-thread va
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38 CHAPTER 4. COUNTING1 unsigned lo
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42 CHAPTER 4. COUNTING1 #define THE
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46 CHAPTER 4. COUNTINGReadsAlgorith
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48 CHAPTER 5. PARTITIONING AND SYNC
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68 CHAPTER 6. LOCKING1 int delete(i
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70 CHAPTER 7. DATA OWNERSHIP
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72 CHAPTER 8. DEFERRED PROCESSINGfo
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110 CHAPTER 9. APPLYING RCU1 struct
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114 CHAPTER 10. VALIDATION: DEBUGGI
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116 CHAPTER 11. DATA STRUCTURES
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138 CHAPTER 13. EASE OF USEFigure 1
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140 CHAPTER 13. EASE OF USE
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142 CHAPTER 14. TIME MANAGEMENT
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144 CHAPTER 15. CONFLICTING VISIONS
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154 APPENDIX A. IMPORTANT QUESTIONS
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156 APPENDIX A. IMPORTANT QUESTIONS
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158 APPENDIX B. SYNCHRONIZATION PRI
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160 APPENDIX B. SYNCHRONIZATION PRI
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162 APPENDIX C. WHY MEMORY BARRIERS
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244 APPENDIX E. FORMAL VERIFICATION
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Page 348 and 349: 336 BIBLIOGRAPHY[But97]USA, March 2
Page 350 and 351: 338 BIBLIOGRAPHY[HMB06][Hol03][HP95
Page 352 and 353: 340 BIBLIOGRAPHY[McK06] Paul E. McK
Page 354 and 355: 342 BIBLIOGRAPHYtor. Software - Pra
Page 356 and 357: 344 BIBLIOGRAPHY[UoC08][VGS08]Berke
Page 358: 346 APPENDIX H. CREDITSH.4 Original
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Is Parallel Programming Hard, And, If So, What Can You Do About It?

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