Is Parallel Programming Hard, And, If So, What Can You Do About It?

C.3. STORES RESULT IN UNNECESSARY STALLS 16710. CPU 0 adds one to the value zero loaded for “a”above, and stores it into the cache line containing“b” (which we will assume is already ownedby CPU 0).11. CPU 0 executes assert(b==2), which fails.The problem is that we have two copies of “a”,one in the cache and the other in the store buffer.This example breaks a very important guarantee,namely that each CPU will always see its ownoperations as if they happened in program order.Breakingthisguaranteeisviolentlycounter-intuitiveto software types, so much so that the hardwareguys took pity and implemented “store forwarding”,where each CPU refers to (or “snoops”) its storebuffer as well as its cache when performing loads, asshown in Figure C.6. In other words, a given CPU’sstores are directly forwarded to its subsequent loads,without having to pass through the cache.CPU 0 CPU 11 void foo(void)2 {3 a = 1;4 b = 1;5 }67 void bar(void)8 {9 while (b == 0) continue;10 assert(a == 1);11 }Suppose CPU 0 executes foo() and CPU 1 executesbar(). Suppose further that the cache linecontaining “a” resides only in CPU 1’s cache, andthat the cache line containing “b” is owned by CPU0. Then the sequence of operations might be as follows:1. CPU 0 executes a=1. The cache line is not inCPU 0’s cache, so CPU 0 places the new valueof “a” in its store buffer and transmits a “readinvalidate” message.2. CPU1executeswhile(b==0)continue, butthecache line containing “b” is not in its cache. Ittherefore transmits a “read” message.CacheStoreBufferCacheStoreBuffer3. CPU 0 executes b=1. It already owns this cacheline (in other words, the cache line is already ineither the “modified” or the “exclusive” state),so it stores the new value of “b” in its cacheline.InterconnectMemoryFigure C.6: Caches With Store ForwardingWithstoreforwardinginplace,item8intheabovesequence would have found the correct value of 1 for“a” in the store buffer, so that the final value of “b”would have been 2, as one would hope.C.3.3 Store Buffers and MemoryBarriersTo see the second complication, a violation of globalmemory ordering, consider the following code sequenceswith variables “a” and “b” initially zero:4. CPU 0 receives the “read” message, and transmitsthe cache line containing the now-updatedvalue of “b” to CPU 1, also marking the line as“shared” in its own cache.5. CPU 1 receives the cache line containing “b”and installs it in its cache.6. CPU 1 can now finish executing while(b==0)continue, and since it finds that the value of“b” is 1, it proceeds to the next statement.7. CPU 1 executes the assert(a==1), and, sinceCPU 1 is working with the old value of “a”, thisassertion fails.8. CPU 1 receives the “read invalidate” message,and transmits the cache line containing “a” toCPU 0 and invalidates this cache line from itsown cache. But it is too late.9. CPU 0 receives the cache line containing “a”and applies the buffered store just in time tofall victim to CPU 1’s failed assertion.