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Revision 2.2Chapter 4 – <strong>SD</strong> <strong>Card</strong> Protocol Description<strong>SanDisk</strong> <strong>SD</strong> <strong>Card</strong> Product ManualData Transfer ModeThere is just one Z bit period followed by P bits pushed up by the responding card. Thistiming diagram is relevant for all responded host commands except CMD1, 2, 3.Command Response Timing (Data Transfer Mode)Host CommandN CRCyclesResponseCMD S T Content CRC E Z Z P *** P S T Content CRC Z E Z Z ZLast <strong>Card</strong> Response—Next Host Command TimingAfter receiving the last card response, the host can start the next command transmissionafter at least N RC clock cycles. This timing is relevant for any host command.Timing Response End to Next CMD Start (Data Transfer Mode)ResponseN RCCyclesHost CommandCMD S T Content CRC E Z ****** Z S T Content CRCZELast Host Command—Next Host Command TimingAfter the last command has been sent, the host can continue sending the next commandafter at least N CC clock periods.Timing of Command Sequences (All modes)Host CommandN CCCyclesHost CommandCMD S T Content CRC E Z ****** Z S T Content CRCZE4.11 Data ReadSingle Block ReadThe host selects one card for data read operation by CMD7 and sets the valid block lengthfor block-oriented data transfer by CMD16. The basic bus timing for a read operation isshown in the Transfer of Single Block Read timing diagram. The sequence starts with asingle block read command, CMD17 that specifies the start address in the argument field.The response is sent on the CMD line as usual.Transfer of Single Block ReadCyclesCMD S T Content CRC E Z Z P *** P S TResponseContent CRC EDAT Z Z Z **** Z Z Z Z Z Z P ********** P S D D D ***N ACCyclesRead DataData transmission from the card starts after the access time delay N AC beginning from theend bit of the read command. After the last data bit, the CRC check bits are suffixed toallow the host to check for transmission errors.© 2004 <strong>SanDisk</strong> Corporation 4-43 12/08/04

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