Nios II Processor Reference Handbook

More documents

Recommendations

Info

Instantiating the Core in SOPC BuilderInstantiating theCore in SOPCBuilderDesigners use the configuration wizard for the SDRAM controller inSOPC Builder to specify hardware features and simulation features. TheSDRAM controller configuration wizard has two tabs: Memory Profileand Timing. This section describes the options available on each tab.The Presets list offers several pre-defined SDRAM configurations as aconvenience. If the SDRAM subsystem on the target board matches oneof the preset configurations, then the SDRAM controller core can beconfigured easily by selecting the appropriate preset value. The followingpreset configurations are defined:■ Micron MT8LSDT1664HG module■ Four SDR100 8 MByte x 16 chips■ Single Micron MT48LC2M32B2-7 chip■ Single Micron MT48LC4M32B2-7 chip■ Single NEC D4564163-A80 chip (64 MByte x 16)■ Single Alliance AS4LC1M16S1-10 chip■ Single Alliance AS4LC2M8S0-10 chipSelecting a preset configuration automatically changes values on theMemory Profile and Timing tabs to match the specific configuration.Altering a configuration setting on any tab changes the Preset value tocustom.5–6 Altera CorporationNios II Processor Reference Handbook September 2004
SDRAM Controller with Avalon InterfaceMemory Profile TabThe Memory Profile tab allows designers to specify the structure of theSDRAM subsystem, such as address and data bus widths, the number ofchip select signals, and the number of banks. Table 5–1 lists the settingsavailable on the Memory Profile tab.Table 5–1. Memory Profile Tab SettingsSettingsAllowedValuesData Width 8, 16, 32,64ArchitectureSettingsAddressWidthSettingsDefaultValuesDescription32 SDRAM data bus width. This value determines the width ofthe dq bus (data) and the dqm bus (byte-enable).Chip Selects 1, 2, 4, 8 1 Number of independent chip selects in the SDRAMsubsystem. By using multiple chip selects, the SDRAMcontroller can combine multiple SDRAM chips into onememory subsystem.Banks 2, 4 4 Number of SDRAM banks. This value determines the widthof the ba bus (bank address) that connects to the SDRAM.The correct value is provided in the data sheet for the targetSDRAM.Row 11, 12,13, 14Column>= 8, andless thanRowvalue12 Number of row address bits. This value determines thewidth of the addr bus. The Row and Column valuesdepend on the geometry of the chosen SDRAM. Forexample, an SDRAM organized as 4096 (2 12 ) rows by 512columns has a Row value of 12.8 Number of column address bits. For example, the SDRAMorganized as 4096 rows by 512 (2 9 ) columns has a Columnvalue of 9.Controller sharesdq/dqm/addr I/O pinsInclude a functional memorymodel in the systemtestbenchYes, No No When set to No, all pins are dedicated to the SDRAM chip.When set to Yes, the addr, dq, and dqm pins can beshared with a tristate bridge in the system. In this case,SOPC Builder presents a new configuration tab that allowsthe user to associate the SDRAM controller pins with aspecific tristate bridge.Yes, No Yes When this option is turned on, SOPC Builder creates afunctional simulation model for the SDRAM chip. Thisdefault memory model accelerates the process of creatingand verifying systems that use the SDRAM controller. See“Hardware Simulation Considerations” on page 5–9.Altera Corporation 5–7September 2004Nios II Processor Reference Handbook
Page 1 and 2: Section II. PeripheralSupportThis s
Page 3 and 4: Chapter(s) Date / Version Changes M
Page 5 and 6: 5. SDRAM Controller withAvalon Inte
Page 7 and 8: SDRAM Controller with Avalon Interf
Page 9: SDRAM Controller with Avalon Interf
Page 19 and 20: 6. DMA Controller withAvalon Interf
Page 21 and 22: DMA Controller with Avalon Interfac
Page 31 and 32: 7. PIO Core With AvalonInterfaceNII
Page 33 and 34: PIO Core With Avalon InterfaceThe h
Page 35 and 36: PIO Core With Avalon InterfaceThe c
Page 37 and 38: PIO Core With Avalon InterfaceLegac
Page 39 and 40: PIO Core With Avalon InterfaceInter
Page 41 and 42: 8. Timer Core with AvalonInterfaceN
Page 43 and 44: Timer Core with Avalon InterfaceDev
Page 45 and 46: Timer Core with Avalon Interface■
Page 47 and 48: Timer Core with Avalon InterfacecTh
Page 49 and 50: Timer Core with Avalon InterfaceWri
Page 51 and 52: 9. JTAG UART Core withAvalon Interf
Page 53 and 54: JTAG UART Core with Avalon Interfac
Page 61 and 62:
JTAG UART Core with Avalon Interfac
Page 63 and 64:
JTAG UART Core with Avalon Interfac
Page 65 and 66:
10. UART Core with AvalonInterfaceN
Page 67 and 68:
UART Core with Avalon InterfaceThe
Page 69 and 70:
UART Core with Avalon InterfaceConf
Page 71 and 72:
UART Core with Avalon Interface■
Page 73 and 74:
UART Core with Avalon Interface■a
Page 75 and 76:
UART Core with Avalon Interface}fpr
Page 77 and 78:
UART Core with Avalon InterfaceLimi
Page 79 and 80:
UART Core with Avalon Interfacetxda
Page 81 and 82:
UART Core with Avalon InterfaceTabl
Page 83 and 84:
UART Core with Avalon InterfaceTabl
Page 85 and 86:
11. SPI Core with AvalonInterfaceNI
Page 87 and 88:
SPI Core with Avalon InterfaceFigur
Page 89 and 90:
SPI Core with Avalon InterfaceMaste
Page 91 and 92:
SPI Core with Avalon InterfaceFigur
Page 93 and 94:
SPI Core with Avalon InterfaceData
Page 95 and 96:
alt_avalon_spi_command()alt_avalon_
Page 97 and 98:
alt_avalon_spi_command()rxdata Regi
Page 99 and 100:
alt_avalon_spi_command()The control
Page 101 and 102:
12. EPCS Device ControllerCore with
Page 103 and 104:
EPCS Device Controller Core with Av
Page 105 and 106:
EPCS Device Controller Core with Av
Page 107 and 108:
13. Common Flash InterfaceControlle
Page 109 and 110:
Common Flash Interface Controller C
Page 111 and 112:
Common Flash Interface Controller C
Page 113 and 114:
14. System ID Core withAvalon Inter
Page 115 and 116:
alt_avalon_sysid_test()alt_avalon_s
Page 117 and 118:
15. Character LCD (Optrex16207) Con
Page 119 and 120:
Character LCD (Optrex 16207) Contro
Page 121 and 122:
16. Mutex Core with AvalonInterface
Page 123 and 124:
Mutex Core with Avalon Interface■
Page 125 and 126:
Mutex Core with Avalon InterfaceMut
Page 127 and 128:
altera_avalon_mutex_first_lock()alt
Page 129 and 130:
altera_avalon_mutex_open()altera_av
Page 131 and 132:
altera_avalon_mutex_unlock()altera_
show all

Nios II Processor Reference Handbook

Create successful ePaper yourself

Delete template?

Save as template?