Nios II Processor Reference Handbook

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Functional DescriptionFigure 5–1. SDRAM Controller with Avalon Interface Block DiagramAltera FPGAPLLClock SkewAdjustmentSDRAM ControllerAvalon slaveinterfaceto on-chiplogicAvalonclockaddressdata, controlwaitrequestreaddatavalidAvalon Slave PortControlLogicInterface to SDRAM pinsckeaddrbacscasraswedqdqmclkPC 100SDRAMThe following sections describe the components of the SDRAM controllercore in detail. All options are specified at system generation time, andcannot be changed at run-time.Avalon InterfaceThe Avalon slave port is the only user-visible part of the SDRAMcontroller core. The slave port presents a flat, contiguous memory spaceas large as the SDRAM chip(s). When accessing the slave port, the detailsof the PC100 SDRAM protocol are entirely transparent. The Avaloninterface behaves as a simple memory interface. There are no memorymappedconfiguration registers.The Avalon slave port supports peripheral-controlled wait-states for readand write transfers. The slave port stalls the transfer until it can presentvalid data. The slave port also supports read transfers with variablelatency, enabling high-bandwidth, pipelined read transfers. When amaster peripheral reads sequential addresses from the slave port, the firstdata returns after an initial period of latency. Subsequent reads canproduce new data every clock cycle. However, data is not guaranteed toreturn every clock cycle, because the SDRAM controller must pauseperiodically to refresh the SDRAM.5–2 Altera CorporationNios II Processor Reference Handbook September 2004
SDRAM Controller with Avalon InterfacefSee the Avalon Interface Specification Reference Manual for details onAvalon transfer types.Off-Chip SDRAM InterfaceThe interface to the external SDRAM chip presents the signals defined bythe PC100 standard. These signals must be connected externally to theSDRAM chip(s) via I/O pins on the Altera FPGA.Signal Timing & Electrical CharacteristicsThe timing and sequencing of signals depends on the configuration of thecore. The hardware designer configures the core to match the SDRAMchip chosen for the system. See “Instantiating the Core in SOPC Builder”on page 5–6 for details. The electrical characteristics of the FPGA pinsdepend on both the target device family and the assignments made in theQuartus ® II software. Some FPGA families support a wider range ofelectrical standards, and therefore are capable of interfacing with agreater variety of SDRAM chips. For details, see the handbook for thetarget FPGA family.SynchronizationThe SDRAM chip is driven at the same clock rate as the Avalon interface.As shown in Figure 5–1, an on-chip phase-locked loop (PLL) is often usedto alleviate clock skew between the SDRAM controller core and theSDRAM chip. At lower clock speeds, the PLL may not be necessary. Athigher clock rates, a PLL becomes necessary to tune the SDRAM clock totoggle within the window when signals are valid on the pins.The PLL block is not an integral part of the SDRAM controller core. If thePLL is necessary, the designer must manually instantiate the PLL outsidethe SOPC Builder-generated system module. Different combinations ofAltera FPGA and SDRAM chip will require different PLL settings.The SDRAM controller does not support clock-disable modes. TheSDRAM controller permanently asserts the cke pin.fThe Nios ® II development kit provides an example hardware design thatuses the SDRAM controller core in conjunction with a PLL.Sharing Pins with Other Avalon Tristate DevicesIf an Avalon tristate bridge is present in the SOPC Builder system, theSDRAM controller core can share pins with the existing tristate bridge. Inthis case, the core’s addr, dq (data) and dqm (byte-enable) pins are sharedwith other devices connected to the Avalon tristate bridge. This featureAltera Corporation 5–3September 2004Nios II Processor Reference Handbook
Page 1 and 2: Section II. PeripheralSupportThis s
Page 3 and 4: Chapter(s) Date / Version Changes M
Page 5: 5. SDRAM Controller withAvalon Inte
Page 9 and 10: SDRAM Controller with Avalon Interf
Page 19 and 20: 6. DMA Controller withAvalon Interf
Page 21 and 22: DMA Controller with Avalon Interfac
Page 31 and 32: 7. PIO Core With AvalonInterfaceNII
Page 33 and 34: PIO Core With Avalon InterfaceThe h
Page 35 and 36: PIO Core With Avalon InterfaceThe c
Page 37 and 38: PIO Core With Avalon InterfaceLegac
Page 39 and 40: PIO Core With Avalon InterfaceInter
Page 41 and 42: 8. Timer Core with AvalonInterfaceN
Page 43 and 44: Timer Core with Avalon InterfaceDev
Page 45 and 46: Timer Core with Avalon Interface■
Page 47 and 48: Timer Core with Avalon InterfacecTh
Page 49 and 50: Timer Core with Avalon InterfaceWri
Page 51 and 52: 9. JTAG UART Core withAvalon Interf
Page 53 and 54: JTAG UART Core with Avalon Interfac
Page 55 and 56: JTAG UART Core with Avalon Interfac
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JTAG UART Core with Avalon Interfac
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10. UART Core with AvalonInterfaceN
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UART Core with Avalon InterfaceThe
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UART Core with Avalon InterfaceConf
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UART Core with Avalon Interface■
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UART Core with Avalon Interface■a
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UART Core with Avalon Interface}fpr
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UART Core with Avalon InterfaceLimi
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UART Core with Avalon Interfacetxda
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UART Core with Avalon InterfaceTabl
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UART Core with Avalon InterfaceTabl
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11. SPI Core with AvalonInterfaceNI
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SPI Core with Avalon InterfaceFigur
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SPI Core with Avalon InterfaceMaste
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SPI Core with Avalon InterfaceFigur
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SPI Core with Avalon InterfaceData
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alt_avalon_spi_command()alt_avalon_
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alt_avalon_spi_command()rxdata Regi
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alt_avalon_spi_command()The control
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12. EPCS Device ControllerCore with
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EPCS Device Controller Core with Av
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EPCS Device Controller Core with Av
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13. Common Flash InterfaceControlle
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Common Flash Interface Controller C
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Common Flash Interface Controller C
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14. System ID Core withAvalon Inter
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alt_avalon_sysid_test()alt_avalon_s
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15. Character LCD (Optrex16207) Con
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Character LCD (Optrex 16207) Contro
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16. Mutex Core with AvalonInterface
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Mutex Core with Avalon Interface■
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Mutex Core with Avalon InterfaceMut
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altera_avalon_mutex_first_lock()alt
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altera_avalon_mutex_open()altera_av
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altera_avalon_mutex_unlock()altera_
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