Nios II Processor Reference Handbook

Functional DescriptionFigure 6–1. X. DMA Controller Block DiagramAvalonslaveportAddr,data,controlIRQControlPortRegister FilestatusreadaddresswriteaddresslengthcontrolReadmasterportWritemasterportSeperateavalonmasterportsA typical DMA transaction proceeds as follows:1. A CPU prepares the DMA controller for a transaction by writing tothe control port.2. The CPU enables the DMA controller. The DMA controller thenbegins transferring data without additional intervention from theCPU. The DMA’s master read port reads data from the read address,which may be a memory or a peripheral. The master write portwrites the data to the destination address, which can also be amemory or peripheral. A shallow FIFO buffers data between theread and write ports.3. The DMA transaction ends when a specified number of bytes aretransferred (i.e., a fixed-length transaction), or an end-of-packetsignal is asserted by either the sender or receiver (i.e., a variablelengthtransaction). At the end of the transaction, the DMAcontroller generates an interrupt request (IRQ) if it was configuredby the CPU to do so.4. During or after the transaction, the CPU can determine if atransaction is in progress, or if the transaction ended (and how) byexamining the DMA controller’s status register.Setting Up DMA TransactionsAn Avalon master peripheral sets up and initiates DMA transactions bywriting to registers via the control port. The master peripheral configuresthe following options:■■Read (source) address locationWrite (destination) address location6–2 Altera CorporationNios II Processor Reference Handbook December 2004