Nios II Processor Reference Handbook

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Example ConfigurationsExampleConfigurationsFigure 7–2 shows a block diagram of the PIO core configured with inputand output ports, as well as support for IRQs.Figure 7–2. PIO Core with Input & Output Ports & with IRQ SupportAvaloninterfaceto on-chiplogicaddressdatacontroldatainout3232interruptmaskIRQedgecaptureFigure 7–3 shows a block diagram of the PIO core configured inbidirectional mode, without support for IRQs.Figure 7–3. PIO Core with Bidirectional PortsAvaloninterfaceto on-chiplogicaddressdatacontroldatainout32directionAvalon InterfaceThe PIO core’s Avalon interface consists of a single Avalon slave port. Theslave port is capable of fundamental Avalon read and write transfers. TheAvalon slave port provides an IRQ output so that the core can assertinterrupts.Instantiating thePIO Core inSOPC BuilderThe hardware feature set is configured via the PIO core’s SOPC Builderconfiguration wizard. The following sections describe the availableoptions.7–4 Altera CorporationNios II Processor Reference Handbook September 2004
PIO Core With Avalon InterfaceThe configuration wizard has two tabs, Basic Settings and InputOptions.Basic SettingsThe Basic Settings tab allows the designer to specify the width anddirection of the I/O ports.■The Width setting can be any integer value between 1 and 32. For avalue of n, the I/O ports become n-bits wide.■ The Direction setting has four options, as shown in Table 7–1.Table 7–1. Direction SettingsSettingBidirectional (tristate) portsInput ports onlyOutput ports onlyBoth input and output portsDescriptionIn this mode, each PIO bit shares one device pin for driving and capturing data.The direction of each pin is individually selectable. To tristate an FPGA I/O pin, setthe direction to input.In this mode the PIO ports can capture input only.In this mode the PIO ports can drive output only.In this mode, the input and output ports buses are separate, unidirectional busesof n bits wide.Input OptionsThe Input Options tab allows the designer to specify edge-capture andIRQ generation settings. The Input Options tab is not available whenOutput ports only is selected on the Basic Settings tab.Edge Capture RegisterWhen the Synchronously capture option is turned on, the PIO corecontains the edge capture register, edgecapture. The user must furtherspecify what type of edge(s) to detect:■■■Rising EdgeFalling EdgeEither EdgeThe edge capture register allows the core to detect and (optionally)generate an interrupt when an edge of the specified type occurs on aninput port.Altera Corporation 7–5September 2004Nios II Processor Reference Handbook
Page 1 and 2: Section II. PeripheralSupportThis s
Page 3 and 4: Chapter(s) Date / Version Changes M
Page 5 and 6: 5. SDRAM Controller withAvalon Inte
Page 7 and 8: SDRAM Controller with Avalon Interf
Page 19 and 20: 6. DMA Controller withAvalon Interf
Page 21 and 22: DMA Controller with Avalon Interfac
Page 31 and 32: 7. PIO Core With AvalonInterfaceNII
Page 33: PIO Core With Avalon InterfaceThe h
Page 37 and 38: PIO Core With Avalon InterfaceLegac
Page 39 and 40: PIO Core With Avalon InterfaceInter
Page 41 and 42: 8. Timer Core with AvalonInterfaceN
Page 43 and 44: Timer Core with Avalon InterfaceDev
Page 45 and 46: Timer Core with Avalon Interface■
Page 47 and 48: Timer Core with Avalon InterfacecTh
Page 49 and 50: Timer Core with Avalon InterfaceWri
Page 51 and 52: 9. JTAG UART Core withAvalon Interf
Page 53 and 54: JTAG UART Core with Avalon Interfac
Page 65 and 66: 10. UART Core with AvalonInterfaceN
Page 67 and 68: UART Core with Avalon InterfaceThe
Page 69 and 70: UART Core with Avalon InterfaceConf
Page 71 and 72: UART Core with Avalon Interface■
Page 73 and 74: UART Core with Avalon Interface■a
Page 75 and 76: UART Core with Avalon Interface}fpr
Page 77 and 78: UART Core with Avalon InterfaceLimi
Page 79 and 80: UART Core with Avalon Interfacetxda
Page 81 and 82: UART Core with Avalon InterfaceTabl
Page 83 and 84: UART Core with Avalon InterfaceTabl
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11. SPI Core with AvalonInterfaceNI
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SPI Core with Avalon InterfaceFigur
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SPI Core with Avalon InterfaceMaste
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SPI Core with Avalon InterfaceFigur
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SPI Core with Avalon InterfaceData
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alt_avalon_spi_command()alt_avalon_
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alt_avalon_spi_command()rxdata Regi
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alt_avalon_spi_command()The control
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12. EPCS Device ControllerCore with
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EPCS Device Controller Core with Av
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EPCS Device Controller Core with Av
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13. Common Flash InterfaceControlle
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Common Flash Interface Controller C
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Common Flash Interface Controller C
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14. System ID Core withAvalon Inter
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alt_avalon_sysid_test()alt_avalon_s
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15. Character LCD (Optrex16207) Con
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Character LCD (Optrex 16207) Contro
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16. Mutex Core with AvalonInterface
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Mutex Core with Avalon Interface■
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Mutex Core with Avalon InterfaceMut
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altera_avalon_mutex_first_lock()alt
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altera_avalon_mutex_open()altera_av
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altera_avalon_mutex_unlock()altera_
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Nios II Processor Reference Handbook

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