Nios II Processor Reference Handbook

More documents

Recommendations

Info

Software Programming ModelTimestamp DriverThe timer core may be used as a timestamp device if it meets thefollowing conditions:■■The timer has a writeable snapshot register, as configured in SOPCBuilder.The timer is not selected as the system clock.The Nios II IDE allows you to specify system library properties thatdetermine which timer device will be used as the timestamp timer.If the timer hardware is not configured with writeable period registers,then calls to the alt_timestamp_start() API function will not resetthe timestamp counter. All other HAL API calls will perform as expected.fSee the Nios II Software Developer’s Handbook for details on using thesystem clock and timestamp features that use these drivers. The Nios IIdevelopment kit also provides several example designs that use thetimer core.LimitationsThe HAL driver for the timer core does not support the watchdog resetfeature of the timer core.Software FilesThe timer core is accompanied by the following software files. These filesdefine the low-level interface to the hardware, and provide the HALdrivers. Application developers should not modify these files.■■altera_avalon_timer_regs.h—This file defines the core’s registermap, providing symbolic constants to access the low-level hardware.altera_avalon_timer.h, altera_avalon_timer_sc.c,altera_avalon_timer_ts.c, altera_avalon_timer_vars.c—These filesimplement the timer device drivers for the HAL system library.Register MapA programmer should never have to directly access the timer via itsregisters if using the standard features provided in the HAL systemlibrary for the Nios II processor. In general, the register map is only usefulto programmers writing a device driver.8–6 Altera CorporationNios II Processor Reference Handbook September 2004
Timer Core with Avalon InterfacecThe Altera-provided HAL device driver accesses the deviceregisters directly. If you are writing a device driver, and theHAL driver is active for the same device, your driver willconflict and fail to operate correctly.Table 8–3 shows the register map for the timer.Table 8–3. Register MapDescription of BitsOffset Name R/W15 ... 4 3 2 1 00 status RW (1) RUN TO1 control RW (1) STOP START CONT ITO2 periodl RW Timeout Period – 1 (bits 15..0)3 periodh RW Timeout Period – 1 (bits 31..16)4 snapl RW Counter Snapshot (bits 15..0)5 snaph RW Counter Snapshot (31..16)Note to Table 8–3:(1) Reserved. Read values are undefined. Write zero.status RegisterThe status register has two defined bits, as shown in Table 8–4.Table 8–4. status Register BitsBitNameRead/Write/ClearDescription0 TO RC The TO (timeout) bit is set to 1 when the internal counter reaches zero. Onceset by a timeout event, the TO bit stays set until explicitly cleared by a masterperipheral. Write zero to the status register to clear the TO bit.1 RUN R The RUN bit reads as 1 when the internal counter is running; otherwise this bitreads as 0. The RUN bit is not changed by a write operation to the statusregister.Altera Corporation 8–7September 2004Nios II Processor Reference Handbook
Page 1 and 2: Section II. PeripheralSupportThis s
Page 3 and 4: Chapter(s) Date / Version Changes M
Page 5 and 6: 5. SDRAM Controller withAvalon Inte
Page 7 and 8: SDRAM Controller with Avalon Interf
Page 19 and 20: 6. DMA Controller withAvalon Interf
Page 21 and 22: DMA Controller with Avalon Interfac
Page 31 and 32: 7. PIO Core With AvalonInterfaceNII
Page 33 and 34: PIO Core With Avalon InterfaceThe h
Page 35 and 36: PIO Core With Avalon InterfaceThe c
Page 37 and 38: PIO Core With Avalon InterfaceLegac
Page 39 and 40: PIO Core With Avalon InterfaceInter
Page 41 and 42: 8. Timer Core with AvalonInterfaceN
Page 43 and 44: Timer Core with Avalon InterfaceDev
Page 45: Timer Core with Avalon Interface■
Page 49 and 50: Timer Core with Avalon InterfaceWri
Page 51 and 52: 9. JTAG UART Core withAvalon Interf
Page 53 and 54: JTAG UART Core with Avalon Interfac
Page 65 and 66: 10. UART Core with AvalonInterfaceN
Page 67 and 68: UART Core with Avalon InterfaceThe
Page 69 and 70: UART Core with Avalon InterfaceConf
Page 71 and 72: UART Core with Avalon Interface■
Page 73 and 74: UART Core with Avalon Interface■a
Page 75 and 76: UART Core with Avalon Interface}fpr
Page 77 and 78: UART Core with Avalon InterfaceLimi
Page 79 and 80: UART Core with Avalon Interfacetxda
Page 81 and 82: UART Core with Avalon InterfaceTabl
Page 83 and 84: UART Core with Avalon InterfaceTabl
Page 85 and 86: 11. SPI Core with AvalonInterfaceNI
Page 87 and 88: SPI Core with Avalon InterfaceFigur
Page 89 and 90: SPI Core with Avalon InterfaceMaste
Page 91 and 92: SPI Core with Avalon InterfaceFigur
Page 93 and 94: SPI Core with Avalon InterfaceData
Page 95 and 96: alt_avalon_spi_command()alt_avalon_
Page 97 and 98:
alt_avalon_spi_command()rxdata Regi
Page 99 and 100:
alt_avalon_spi_command()The control
Page 101 and 102:
12. EPCS Device ControllerCore with
Page 103 and 104:
EPCS Device Controller Core with Av
Page 105 and 106:
EPCS Device Controller Core with Av
Page 107 and 108:
13. Common Flash InterfaceControlle
Page 109 and 110:
Common Flash Interface Controller C
Page 111 and 112:
Common Flash Interface Controller C
Page 113 and 114:
14. System ID Core withAvalon Inter
Page 115 and 116:
alt_avalon_sysid_test()alt_avalon_s
Page 117 and 118:
15. Character LCD (Optrex16207) Con
Page 119 and 120:
Character LCD (Optrex 16207) Contro
Page 121 and 122:
16. Mutex Core with AvalonInterface
Page 123 and 124:
Mutex Core with Avalon Interface■
Page 125 and 126:
Mutex Core with Avalon InterfaceMut
Page 127 and 128:
altera_avalon_mutex_first_lock()alt
Page 129 and 130:
altera_avalon_mutex_open()altera_av
Page 131 and 132:
altera_avalon_mutex_unlock()altera_
show all

Nios II Processor Reference Handbook

Create successful ePaper yourself

Delete template?

Save as template?