Nios II Processor Reference Handbook

Functional Descriptionconserves I/O pins, which is valuable in systems that have multipleexternal memory chips (e.g., flash, SRAM, in addition to SDRAM), buttoo few pins to dedicate to the SDRAM chip. See “PerformanceConsiderations” on page 5–4 for details on how pin sharing affectsperformance.Performance ConsiderationsUnder optimal conditions, the SDRAM controller core’s bandwidthapproaches one word per clock cycle. However, because of the overheadassociated with refreshing the SDRAM, it is impossible to reach one wordper clock cycle. Other factors affect the core’s performance, as describedbelow.Open Row ManagementSDRAM chips are arranged as multiple banks of memory, wherein eachbank is capable of independent open-row address management. TheSDRAM controller core takes advantage of open-row management for asingle bank. Continuous reads or writes within the same row and bankwill operate at rates approaching one word per clock. Applications thatfrequently access different destination banks will require extramanagement cycles for row closings and openings.Sharing Data & Address PinsWhen the controller shares pins with other tristate devices, average accesstime usually increases while bandwidth decreases. When access to thetristate bridge is granted to other devices, the SDRAM requires row openand close overhead cycles. Furthermore, the SDRAM controller has towait several clock cycles before it is granted access again.To maximize bandwidth, the SDRAM controller automatically maintainscontrol of the tristate bridge as long as back-to-back read or writetransactions continue within the same row and bank.1 Note that this behavior may degrade the average access time forother devices sharing the Avalon tristate bridge.The SDRAM controller closes an open row whenever there is a break inback-to-back transactions, or whenever a refresh transaction is required.As a result:■■The controller cannot permanently block access to other devicessharing the tristate bridge.The controller is guaranteed not to violate the SDRAM’s row opentime limit.5–4 Altera CorporationNios II Processor Reference Handbook September 2004