Nios II Processor Reference Handbook

Software Programming ModelTable 6–3. DMA Controller Register MapOff-setRegisterName2 writeaddressRead/WriteRW31. . .11Write master start address3 length RW DMA transaction length (in bytes)4 - Reserved (3)5 - Reserved (3)6 control RW (2) (4)(5)WCONRCONLEENWEEN7 - Reserved (3)109 8 7 6 5 4 3 2 1 0REENNotes:(1) Writing zero to the status register clears the LEN, WEOP, REOP, and DONE bits.(2) These bits are reserved. Read values are undefined. Write zero.(3) This register is reserved. Read values are undefined. The result of a write is undefined.(4) QUADWORD.(5) DOUBLEWORD.I_ENGOWORDHWBYTEstatus RegisterThe status register consists of individual bits that indicate conditionsinside the DMA controller. The status register can be read at any time.Reading the status register does not change its value.The status register bits are shown in Table 6–4.Table 6–4. status Register BitsBit Number Bit Name Read/Write/Clear Description0 DONE R/C A DMA transaction is completed. The DONE bit is set to 1 whenan end of packet condition is detected or the specifiedtransaction length is completed. Write zero to the status registerto clear the DONE bit.1 BUSY R The BUSY bit is 1 when a DMA transaction is in progress.2 REOP R The REOP bit is 1 when a transaction is completed due to anend-of-packet event on the read side.3 WEOP R The WEOP bit is 1 when a transaction is completed due to anend of packet event on the write side.4 LEN R The LEN bit is set to 1 when the length register decrements tozero.6–8 Altera CorporationNios II Processor Reference Handbook December 2004