Nios II Processor Reference Handbook

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Example ConfigurationsFigure 5–3 shows two 64-Mbit SDRAM chips, each with 16-bit data.Address and control signals wire in parallel to both chips. Note thatchipselect (cs_n) is shared by the chips. Each chip provides half of the 32-bit data bus. The result is a logical 128-Mbit (16-Mbyte) 32-bit datamemory.Figure 5–3. Two 64-MBit SDRAM Chips Each with 16-Bit DataAltera FPGASDRAMControlleraddrctlcs_n64 Mbits8 Mbytes16 data width device16Avaloninterfacetoon-chiplogic64 Mbits8 Mbytes16 data width device16data325–12 Altera CorporationNios II Processor Reference Handbook September 2004
SDRAM Controller with Avalon InterfaceFigure 5–4 shows two 128-Mbit SDRAM chips, each with 32-bit data.Control, address and data signals wire in parallel to the two chips. Thechipselect bus (cs_n[1:0]) determines which chip is selected. The resultis a logical 256-Mbit 32-bit wide memory.Figure 5–4. Two 128-Mbit SDRAM Chips Each with 32-Bit DataAltera FPGASDRAMControlleraddrctlcs_n [0]128 Mbits16 Mbytes32 data width device32Avaloninterfacetoon-chiplogic128 Mbits16 Mbytes32 data width device32cs_n [1]data 32SoftwareProgrammingModelThe SDRAM controller behaves like simple memory when accessed viathe Avalon interface. There are no software-configurable settings, andthere are no memory-mapped registers. No software driver routines arerequired for a processor to access the SDRAM controller.Altera Corporation 5–13September 2004Nios II Processor Reference Handbook
Page 1 and 2: Section II. PeripheralSupportThis s
Page 3 and 4: Chapter(s) Date / Version Changes M
Page 5 and 6: 5. SDRAM Controller withAvalon Inte
Page 7 and 8: SDRAM Controller with Avalon Interf
Page 15: SDRAM Controller with Avalon Interf
Page 19 and 20: 6. DMA Controller withAvalon Interf
Page 21 and 22: DMA Controller with Avalon Interfac
Page 31 and 32: 7. PIO Core With AvalonInterfaceNII
Page 33 and 34: PIO Core With Avalon InterfaceThe h
Page 35 and 36: PIO Core With Avalon InterfaceThe c
Page 37 and 38: PIO Core With Avalon InterfaceLegac
Page 39 and 40: PIO Core With Avalon InterfaceInter
Page 41 and 42: 8. Timer Core with AvalonInterfaceN
Page 43 and 44: Timer Core with Avalon InterfaceDev
Page 45 and 46: Timer Core with Avalon Interface■
Page 47 and 48: Timer Core with Avalon InterfacecTh
Page 49 and 50: Timer Core with Avalon InterfaceWri
Page 51 and 52: 9. JTAG UART Core withAvalon Interf
Page 53 and 54: JTAG UART Core with Avalon Interfac
Page 65 and 66: 10. UART Core with AvalonInterfaceN
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UART Core with Avalon InterfaceThe
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UART Core with Avalon InterfaceConf
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UART Core with Avalon Interface■
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UART Core with Avalon Interface■a
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UART Core with Avalon Interface}fpr
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UART Core with Avalon InterfaceLimi
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UART Core with Avalon Interfacetxda
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UART Core with Avalon InterfaceTabl
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UART Core with Avalon InterfaceTabl
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11. SPI Core with AvalonInterfaceNI
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SPI Core with Avalon InterfaceFigur
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SPI Core with Avalon InterfaceMaste
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SPI Core with Avalon InterfaceFigur
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SPI Core with Avalon InterfaceData
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alt_avalon_spi_command()alt_avalon_
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alt_avalon_spi_command()rxdata Regi
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alt_avalon_spi_command()The control
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12. EPCS Device ControllerCore with
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EPCS Device Controller Core with Av
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EPCS Device Controller Core with Av
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13. Common Flash InterfaceControlle
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Common Flash Interface Controller C
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Common Flash Interface Controller C
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14. System ID Core withAvalon Inter
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alt_avalon_sysid_test()alt_avalon_s
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15. Character LCD (Optrex16207) Con
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Character LCD (Optrex 16207) Contro
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16. Mutex Core with AvalonInterface
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Mutex Core with Avalon Interface■
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Mutex Core with Avalon InterfaceMut
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altera_avalon_mutex_first_lock()alt
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altera_avalon_mutex_open()altera_av
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altera_avalon_mutex_unlock()altera_
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