Nios II Processor Reference Handbook

Software Programming ModelTable 6–5. control Register Bits (Part 2 of 2)Bit Number Bit Name Read/Write/Clear Description3 GO RW Enables DMA transaction. When the GO bit is set to 0,the DMA is prevented from executing transfers. Whenthe GO bit is set to 1 and the length register is non-zero,transfers occur.4 I_EN RW Enables interrupt requests (IRQ). When the I_EN bit is 1,the DMA controller generates an IRQ when the statusregister’s DONE bit is set to 1. IRQs are disabled whenthe I_EN bit is 0.5 REEN RW Ends transaction on read-side end-of-packet. When theREEN bit is set to 1, a streaming slave port on the readside may end the DMA transaction by asserting its endof-packetsignal.6 WEEN RW Ends transaction on write-side end-of-packet. When theWEEN bit is set to 1, a streaming slave port on the writeside may end the DMA transaction by asserting its endof-packetsignal.7 LEEN RW Ends transaction when the length register reacheszero. When the LEEN bit is 1, the DMA transaction endswhen the length register reaches 0. When this bit is 0,length reaching 0 does not cause a transaction toend. In this case, the DMA transaction must beterminated by an end-of-packet signal from either theread or write master port.8 RCON RW Reads from a constant address. When RCON is 0, theread address increments after every data transfer. Thisis the mechanism for the DMA controller to read a rangeof memory addresses. When RCON is 1, the readaddress does not increment. This is the mechanism forthe DMA controller to read from a peripheral at aconstant memory address. For details, see “AddressIncrementing” on page 6–3.9 WCON RW Writes to a constant address. Similar to the RCON bit,when WCON is 0 the write address increments afterevery data transfer; when WCON is 1 the write addressdoes not increment. For details, see “AddressIncrementing” on page 6–3.10 DOUBLEWORD RW Specifies doubleword transfers.11 QUADWORD RW Specifies quadword transfers.The data width of DMA transactions is specified by the BYTE, HW,WORD, DOUBLEWORD, and QUADWORD bits. Only one of these bitscan be set at a time. If more than one of the bits is set, the DMA controllerbehavior is undefined. The width of the transfer is determined by the6–10 Altera CorporationNios II Processor Reference Handbook December 2004