Nios II Processor Reference Handbook

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Software Programming Model6–12 Altera CorporationNios II Processor Reference Handbook December 2004
7. PIO Core With AvalonInterfaceNII51007-1.1Core OverviewThe parallel input/output (PIO) core provides a memory-mappedinterface between an Avalon slave port and general-purpose I/O ports.The I/O ports connect either to on-chip user logic, or to I/O pins thatconnect to devices external to the FPGA.The PIO core provides easy I/O access to user logic or external devices insituations where a “bit banging” approach is sufficient. Some exampleuses are:■■■■Controlling LEDsAcquiring data from switchesControlling display devicesConfiguring and communicating with off-chip devices, such asapplication-specific standard products (ASSP)The PIO core interrupt request (IRQ) output can assert an interrupt basedon input signals. The PIO core is SOPC Builder ready and integrateseasily into any SOPC Builder-generated system.FunctionalDescriptionEach PIO core can provide up to 32 I/O ports. An intelligent host such asa microprocessor controls the PIO ports by reading and writing theregister-mapped Avalon interface. Under control of the host, the PIO corecaptures data on its inputs and drives data to its outputs. When the PIOports are connected directly to I/O pins, the host can tristate the pins bywriting control registers in the PIO core. Figure 7–1 shows an example ofa processor-based system that uses multiple PIO cores to blink LEDs,capture edges from on-chip reset-request control logic, and control an offchipLCD display.Altera Corporation 7–1September 2004
Page 1 and 2: Section II. PeripheralSupportThis s
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Page 43 and 44: Timer Core with Avalon InterfaceDev
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Page 75 and 76: UART Core with Avalon Interface}fpr
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UART Core with Avalon InterfaceTabl
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UART Core with Avalon InterfaceTabl
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11. SPI Core with AvalonInterfaceNI
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SPI Core with Avalon InterfaceFigur
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SPI Core with Avalon InterfaceMaste
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SPI Core with Avalon InterfaceFigur
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SPI Core with Avalon InterfaceData
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alt_avalon_spi_command()alt_avalon_
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alt_avalon_spi_command()rxdata Regi
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alt_avalon_spi_command()The control
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12. EPCS Device ControllerCore with
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EPCS Device Controller Core with Av
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EPCS Device Controller Core with Av
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13. Common Flash InterfaceControlle
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Common Flash Interface Controller C
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Common Flash Interface Controller C
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14. System ID Core withAvalon Inter
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alt_avalon_sysid_test()alt_avalon_s
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15. Character LCD (Optrex16207) Con
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Character LCD (Optrex 16207) Contro
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16. Mutex Core with AvalonInterface
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Mutex Core with Avalon Interface■
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Mutex Core with Avalon InterfaceMut
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altera_avalon_mutex_first_lock()alt
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altera_avalon_mutex_open()altera_av
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altera_avalon_mutex_unlock()altera_
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