Nios II Processor Reference Handbook

More documents

Recommendations

Info

Functional DescriptionThe timer core has two user-visible features:■■The Avalon interface that provides access to six 16-bit registersAn optional pulse output that can be used as a periodic pulsegeneratorAll registers are 16-bits wide, making the timer compatible with both 16-bit and 32-bit processors. Certain registers only exist in hardware for agiven configuration. For example, if the timer is configured with a fixedperiod, the period registers do not exist in hardware.The basic behavior of the timer is described below:■■■■■■An Avalon master peripheral, such as a Nios II processor, writes thetimer core’s control register to:● Start and stop the timer● Enable/disable the IRQ● Specify count-down once or continuous count-down modeA processor reads the status register for information about currenttimer activity.A processor can specify the timer period by writing a value to theperiod registers, periodl and periodh.An internal counter counts down to zero, and whenever it reacheszero, it is immediately reloaded from the period registers.A processor can read the current counter value by first writing toeither snapl or snaph to request a coherent snapshot of the counter,and then reading snapl and snaph for the full 32-bit value.When the count reaches zero:● If IRQs are enabled, an IRQ is generated● The (optional) pulse-generator output is asserted for one clockperiod● The (optional) watchdog output resets the systemAvalon Slave InterfaceThe timer core implements a simple Avalon slave interface to provideaccess to the register file. The Avalon slave port uses the resetrequestsignal to implement watchdog timer behavior. This signal is a nonmaskablereset signal, and it drives the reset input of all Avalonperipherals in the SOPC Builder system. When the resetrequestsignal is asserted, it forces any processor connected to the system toreboot. See “Configuring the Timer as a Watchdog Timer” on page 8–4 forfurther details.8–2 Altera CorporationNios II Processor Reference Handbook September 2004
Timer Core with Avalon InterfaceDevice & ToolsSupportInstantiating theCore in SOPCBuilderThe timer core supports all Altera ® FPGA families.Designers use the timer’s SOPC Builder configuration wizard to specifythe hardware features. This section describes the options available in theconfiguration wizard.Timeout PeriodThe Timeout Period setting determines the initial value of the periodland periodh registers. When the Writeable period setting is enabled, aprocessor can change the value of the period by writing periodl andperiodh. When the Writeable period setting (see below) is turned off,the period is fixed and cannot be updated at runtime.The Timeout Period setting can be specified in units of usec, msec, sec, orclocks (number of clock cycles). The actual period achieved depends onthe system clock. If the period is specified in usec, msec or sec, the trueperiod will be the smallest number of clock cycles that is greater than orequal to the specified Timeout Period.Hardware OptionsThe following options affect the hardware structure of the timer core. Asa convenience, the Preset Configurations list offers several pre-definedhardware configurations, such as:■■■Simple periodic interrupt—This configuration is useful for systemsthat require only a periodic IRQ generator. The period is fixed andthe timer cannot be stopped, but the IRQ can be disabled.Full-featured—This configuration is useful for embedded processorsystems that require a timer with variable period that can be startedand stopped under processor control.Watchdog—This configuration is useful for systems that requirewatchdog timer to reset the system in the event that the system hasstopped responding. See “Configuring the Timer as a WatchdogTimer” on page 8–4.Altera Corporation 8–3September 2004Nios II Processor Reference Handbook
Page 1 and 2: Section II. PeripheralSupportThis s
Page 3 and 4: Chapter(s) Date / Version Changes M
Page 5 and 6: 5. SDRAM Controller withAvalon Inte
Page 7 and 8: SDRAM Controller with Avalon Interf
Page 19 and 20: 6. DMA Controller withAvalon Interf
Page 21 and 22: DMA Controller with Avalon Interfac
Page 31 and 32: 7. PIO Core With AvalonInterfaceNII
Page 33 and 34: PIO Core With Avalon InterfaceThe h
Page 35 and 36: PIO Core With Avalon InterfaceThe c
Page 37 and 38: PIO Core With Avalon InterfaceLegac
Page 39 and 40: PIO Core With Avalon InterfaceInter
Page 41: 8. Timer Core with AvalonInterfaceN
Page 45 and 46: Timer Core with Avalon Interface■
Page 47 and 48: Timer Core with Avalon InterfacecTh
Page 49 and 50: Timer Core with Avalon InterfaceWri
Page 51 and 52: 9. JTAG UART Core withAvalon Interf
Page 53 and 54: JTAG UART Core with Avalon Interfac
Page 65 and 66: 10. UART Core with AvalonInterfaceN
Page 67 and 68: UART Core with Avalon InterfaceThe
Page 69 and 70: UART Core with Avalon InterfaceConf
Page 71 and 72: UART Core with Avalon Interface■
Page 73 and 74: UART Core with Avalon Interface■a
Page 75 and 76: UART Core with Avalon Interface}fpr
Page 77 and 78: UART Core with Avalon InterfaceLimi
Page 79 and 80: UART Core with Avalon Interfacetxda
Page 81 and 82: UART Core with Avalon InterfaceTabl
Page 83 and 84: UART Core with Avalon InterfaceTabl
Page 85 and 86: 11. SPI Core with AvalonInterfaceNI
Page 87 and 88: SPI Core with Avalon InterfaceFigur
Page 89 and 90: SPI Core with Avalon InterfaceMaste
Page 91 and 92: SPI Core with Avalon InterfaceFigur
Page 93 and 94:
SPI Core with Avalon InterfaceData
Page 95 and 96:
alt_avalon_spi_command()alt_avalon_
Page 97 and 98:
alt_avalon_spi_command()rxdata Regi
Page 99 and 100:
alt_avalon_spi_command()The control
Page 101 and 102:
12. EPCS Device ControllerCore with
Page 103 and 104:
EPCS Device Controller Core with Av
Page 105 and 106:
EPCS Device Controller Core with Av
Page 107 and 108:
13. Common Flash InterfaceControlle
Page 109 and 110:
Common Flash Interface Controller C
Page 111 and 112:
Common Flash Interface Controller C
Page 113 and 114:
14. System ID Core withAvalon Inter
Page 115 and 116:
alt_avalon_sysid_test()alt_avalon_s
Page 117 and 118:
15. Character LCD (Optrex16207) Con
Page 119 and 120:
Character LCD (Optrex 16207) Contro
Page 121 and 122:
16. Mutex Core with AvalonInterface
Page 123 and 124:
Mutex Core with Avalon Interface■
Page 125 and 126:
Mutex Core with Avalon InterfaceMut
Page 127 and 128:
altera_avalon_mutex_first_lock()alt
Page 129 and 130:
altera_avalon_mutex_open()altera_av
Page 131 and 132:
altera_avalon_mutex_unlock()altera_
show all

Nios II Processor Reference Handbook

Create successful ePaper yourself

Delete template?

Save as template?