HLASM: V1R6 Language Ref

Examples of coded machine instructionsRIformatThe operand fields of RI-format instructions designate a register and an immediateoperand, with the following exception:v In BRC branching instructions, a 4-bit branching mask with a value between 0and 15 inclusive replaces the register designation.Symbols used to represent registers (such as REG1 in the example) are assumed tobe equated to absolute values between 0 and 15. The 16-bit immediate operand hastwo different interpretations, depending on whether the instruction is a branchinginstruction or not.There are two types of non-branching RI-format instructions.v For most, the immediate value is treated as a signed binary integer (a valuebetween −32768 and +32767). This value may be specified using self-definingterms or equated symbols.┌────────┬────┬────┬─────────────────┐│Op Code │ R₁ │OpCd│ I₂ │└────────┴────┴────┴─────────────────┘0 8 12 16 31v For logical instructions such as TMH, the immediate field is a 16 bit mask.┌────────┬────┬────┬─────────────────┐│Op Code │ M₁ │OpCd│ I₂ │└────────┴────┴────┴─────────────────┘0 8 12 16 31Examples:ALPHA1 AHI REG1,2000ALPHA2 MHI 3,1234BETA1 TMH 7,X’8001’When assembled, the object code for the instruction labeled BETA1, inhexadecimal, isA7708001where:A7.0 is the operation code7 is register R₁8001 is the immediate data I2For branching RI-format instructions, the immediate value is treated as a signedbinary integer representing the number of halfwords to branch relative to thecurrent location.The branch target may be specified as a relocatable expression, in which case theassembler performs some checking, and calculates the immediate value.The branch target may also be specified as an absolute value in which case theassembler issues a warning before it assembles the instruction.Examples:ALPHA1 BRAS 1,BETA1ALPHA2 BRC 3,ALPHA1BETA1 BRCT 7,ALPHA1When assembled, the object code for the instruction labeled BETA1, inhexadecimal, is88 HLASM: V1R6 Language Ref