HLASM: V1R6 Language Ref

Examples of coded machine instructionsIn BC branching instructions, a 4-bit branching mask (see 7 and TEN in theinstructions labeled LAMBDAn below) with a value between 0 and 15, replacesthe first register specification.┌────────┬────┬────┬────┬────────────┐│Op Code │ R₁ │ X₂ │ B₂ │ D₂ │└────────┴────┴────┴────┴────────────┘0 8 12 16 20 31Symbols used to represent registers (see REG1, INDEX, and BASE in the ALPHA2instruction below) are assumed to be equated to absolute values between 0 and 15.Symbols used to represent implicit addresses (see IMPLICIT in the instructionslabeled GAMMAn below) can be either relocatable or absolute.Symbols used to represent displacements (see DISPL in the instructions labeledBETA2 and LAMBDA1 below) in explicit addresses are assumed to be equated toabsolute values between 0 and 4095.Examples:ALPHA1 L 1,200(4,10)ALPHA2 L REG1,200(INDEX,BASE)BETA1 L 2,200(,10)BETA2 L REG2,DISPL(,BASE)GAMMA1 L 3,IMPLICITGAMMA2 L 3,IMPLICIT(INDEX)DELTA1 L 4,=F’33’LAMBDA1 BC 7,DISPL(,BASE)LAMBDA2 BC TEN,ADDRESSWhen assembled, the object code for the instruction labeled ALPHA1, inhexadecimal, is:5814A0C8where:58 is the operation code1 is register R₁4 is index register X₂A is base register B₂0C8 is displacement D₂ from base register B₂When assembled, the object code for the instruction labeled GAMMA1, inhexadecimal, is:5824xyyywhere:58 is the operation code2 is register R₁4 is the index register X₂x is base register B₂yyy is displacement D₂ from base register B₂SIformatThe operand fields of SI-format instructions designate immediate data and avirtual storage address.92 HLASM: V1R6 Language Ref