HLASM: V1R6 Language Ref

Examples of coded machine instructionsALPHA1 LR 1,2ALPHA2 LR INDEX,REG2GAMMA1 BCR 8,12DELTA1 SVC 200DELTA2 SVC TENWhen assembled, the object code of the instruction labeled ALPHA1, in hexadecimal,is:1812where:18 is the operation code1 is register R₁2 is register R₂RSformatThe operand fields of RS-format instructions designate two registers, and a virtualstorage address (coded as an implicit address or an explicit address).┌────────┬────┬────┬────┬────────────┐│Op Code │ R₁ │ R₃ │ B₂ │ D₂ │└────────┴────┴────┴────┴────────────┘0 8 12 16 20 31In the Insert Characters under Mask (ICM) and the Store Characters under Mask(STCM) instructions, a 4-bit mask (see X’E’ and MASK in the instructions labeledDELTA1 and DELTA2 below), with a value between 0 and 15, replaces the secondregister specifications.┌────────┬────┬────┬────┬────────────┐│Op Code │ R₁ │ M₃ │ B₂ │ D₂ │└────────┴────┴────┴────┴────────────┘0 8 12 16 20 31Symbols used to represent registers (see REG4, REG6, and BASE in the instructionlabeled ALPHA2 below) are assumed to be equated to absolute values between 0 and15.Symbols used to represent implicit addresses (see AREA and IMPLICIT in theinstructions labeled BETA1 and DELTA2 below) can be either relocatable or absolute.Symbols used to represent displacements (see DISPL in the instruction labeledBETA2 below) in explicit addresses are assumed to be equated to absolute valuesbetween 0 and 4095.Examples:ALPHA1 LM 4,6,20(12)ALPHA2 LM REG4,REG6,20(BASE)BETA1 STM 4,6,AREABETA2 STM 4,6,DISPL(BASE)GAMMA1 SLL 2,15DELTA1 ICM 3,X’E’,1024(10)DELTA2 ICM REG3,MASK,IMPLICITWhen assembled, the object code for the instruction labeled ALPHA1, inhexadecimal, is:9846C014where:90 HLASM: V1R6 Language Ref