PowerPC 740 and PowerPC 750 Microprocessor Datasheet - IBM

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PowerPC 740 and PowerPC 750 MicroprocessorCMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.260x Bus Output AC SpecificationsThe following table provides the 60x bus output AC timing specifications for the 750 as defined in Figure 6.Output timing specification for the L2 bus are provided in the “L2 Bus Output AC Specifications,” on page 23.60X Bus Output AC Timing Specifications for the 750 1See ”Recommended Operating Conditions,” on page 11 for operating conditions, C L = 50pF 2Num Characteristic All Frequencies Unit NotesMinimumMaximum12 SYSCLK to Output Driven (Output Enable Time) 0.5 ns 813 SYSCLK to Output Valid (TS, ABB, ARTRY, DBB, and TBST) – 4.5 ns 514 SYSCLK to all other Output Valid (all except TS, ABB, ARTRY,DBB, and TBST)– 5.0 ns 515 SYSCLK to Output Invalid (Output Hold) 1.0 ns 3, 8, 916 SYSCLK to Output High Impedance (all signals except ABB,ARTRY, and DBB)– 6.0 ns 817 SYSCLK to ABB and DBB high impedance after precharge – 1.0 t SYSCLK 4, 6, 818 SYSCLK to ARTRY high impedance before precharge – 5.5 ns 819 SYSCLK to ARTRY precharge enable 0.2×t SYSCLK + 1.0 ns 3, 4, 720 Maximum delay to ARTRY precharge 1 t SYSCLK 4, 721 SYSCLK to ARTRY high impedance after precharge 2 t SYSCLK 4, 7, 8Note:1. All output specifications are measured from Vm of the rising edge of SYSCLK to Vm of the signal in question. Both input and output timings are measuredat the pin.2. All maximum timing specifications assume C L = 50pF.3. This minimum parameter assumes CL = 0pF.4. t SYSCLK is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period ofSYSCLK to compute the actual time duration of the parameter in question.5. This footnote has been deleted.6. Nominal precharge width for ABB and DBB is 0.5 t SYSCLK .7. Nominal precharge width for ARTRY is 1.0 t SYSCLK .8. Guaranteed by design and characterization, and not tested.9. Connecting L2_TSTCLK to GND no longer provides additional Output Hold. For new designs, L2_TSTCLK should be pulled up to OV DD , but it can beleft connected to GND in Legacy systems.9/6/2002 Version 2.0 Page 18
PowerPC 740 and PowerPC 750 MicroprocessorCMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2Figure 6. Output Timing DiagramVMVMVMSYSCLK1415All Outputs(Except TS,ABB, DBB,ARTRY)12VM16VM13151316TSVM17ABB, DBB212019ARTRY18Vm = 1.4 V for OV DD = 3.3 V., else Vm = OV DD /2Page 19 Version 2.0 9/6/2002
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PowerPC 740 and PowerPC 750 Microprocessor Datasheet - IBM

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