PowerPC 740 and PowerPC 750 Microprocessor Datasheet - IBM

PowerPC 740 and PowerPC 750 MicroprocessorCMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2PLL ConfigurationThe 750 PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the PLL configurationsignals set the internal CPU and VCO frequency of operation.PLL ConfigurationPLL_CFG(0:3)Processor to Bus Frequency Ratiobindec0000 0 Rsv 10001 1 7.5x0010 2 7x0011 3 PLL Bypass 30100 4 2x 60101 5 6.5x0110 6 10x0111 7 4.5x1000 8 3x1001 9 5.5x1010 10 4x1011 11 5x1100 12 8x1101 13 6x1110 14 3.5x1111 15 Off 4Note:1. Reserved settings.2. SYSCLK min is limited by the lowest frequency that manufacturing will support, see Section , “Clock AC Specifications,” for valid SYSCLK and VCOfrequencies.3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 modeoperation. This mode is intended for factory use only. Note: The AC timing specifications given in the document do not apply in PLL-bypass mode.4. In Clock-off mode, no clocking occurs inside the 750 regardless of the SYSCLK input.5. The VCO to core clock ratio is 2x for 740/750. This simplifies clock frequency calculations so the user can disregard the VCO frequency. The VCO willoperate correctly when the core clock is within specification.6. Not tested.9/6/2002 Version 2.0 Page 40