PowerPC 740 and PowerPC 750 Microprocessor Datasheet - IBM

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PowerPC 740 and PowerPC 750 MicroprocessorCMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2Figure 9. L2 Bus Output Timing DiagramsL2SYNC_INVMVM2627ALL OUTPUTSVMVM28L2DATA BUSVm = 1.4 V for L2OV DD = 3.3 V., else Vm = L2OV DD /29/6/2002 Version 2.0 Page 24
PowerPC 740 and PowerPC 750 MicroprocessorCMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2IEEE 1149.1 AC Timing SpecificationsThe table below provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 10,Figure 11, Figure 12, and Figure 13. The five JTAG signals are; TDI, TDO, TMS, TCK, and TRST.JTAG AC Timing Specifications (Independent of SYSCLK)See ”Recommended Operating Conditions,” on page 11 for operating conditions, C L = 50pF.Num Characteristic Min Max Unit NotesTCK frequency of operation 0 25 MHz1 TCK cycle time 40 — ns2 TCK clock pulse width measured at 1.4V 15 — ns3 TCK rise and fall times 0 2 ns 44 spec obsolete, intentionally omitted5 TRST assert time 25 — ns 16 Boundary-scan input data setup time 4 — ns 27 Boundary-scan input data hold time 16 — ns 28 TCK to output data valid 4 20 ns 3, 59 TCK to output high impedance 3 19 ns 3, 410 TMS, TDI data setup time 0 — ns11 TMS, TDI data hold time 16 — ns12 TCK to TDO data valid 2.5 12 ns 513 TCK to TDO high impedance 3 9 ns 4Note:1. TRST is an asynchronous level sensitive signal. Guaranteed by design.2. Non-JTAG signal input timing with respect to TCK.3. Non-JTAG signal output timing with respect to TCK.4. Guaranteed by characterization and not tested.5. Minimum spec guaranteed by characterization and not tested.Figure 10. JTAG Clock Input Timing Diagram12 2TCK VM VMVM3 3Vm = 1.4 V for OV DD = 3.3 V., else Vm = OV DD /2Page 25 Version 2.0 9/6/2002
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PowerPC 740 and PowerPC 750 Microprocessor Datasheet - IBM

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