PowerPC 740 and PowerPC 750 Microprocessor Datasheet - IBM

PowerPC 740 and PowerPC 750 MicroprocessorCMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2L2 Bus Output AC SpecificationsL2 Bus Output Interface AC Timing Specifications 1See ”Recommended Operating Conditions,” on page 11 for operating conditions, C L = 20pF 3 .Num Characteristic L2CR[14:15] is equivalent to: Unit Notes00 2 01 10 11Min Max Min Max Min Max Min Max26 L2SYNC_IN to output valid,Fmax 7 up through 375 MHz.26 L2SYNC_IN to output valid, Fmax= 400 MHz.26 L2SYNC_IN to output valid, Fmax= 433 and 450 MHz.26 L2SYNC_IN to output valid, Fmax= 466 and above.— 3.2 — 3.7 — Rsv 5 — Rsv 5 ns— 3.0 — 3.5 — Rsv 5 — Rsv 5 ns— 2.6 — 3.1 — Rsv 5 — Rsv 5 ns— 2.4 — 2.9 — Rsv 5 — Rsv 5 ns27 L2SYNC_IN to output hold 0.5 — 1.0 — Rsv 5 — Rsv 5 — ns 4, 628 L2SYNC_IN to high impedance — 3.5 — 4.0 — Rsv 5 — Rsv 5 ns 6Note:1. All outputs are measured from the Vm of the rising edge of L2SYNC_IN to the Vm of the signal in question. The output timings are measured at the pins(see Figure 9).2. The outputs are valid for both single-ended and differential L2CLK modes. For flow-through and pipelined reg-reg synchronous burst SRAMs,L2CR[14:15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14:15] = 01 is recommended.3. All maximum timing specifications assume C L = 20pF.4. This measurement assumes C L = 5pF.5. Reserved for future use.6. Guaranteed by design and characterization, and not tested.7. Specifications are shown as a Function of Maximum Core Frequency (Fmax). They refer to the effective Fmax of the part after derating for applicationconditions. For example, a nominal 450 MHz part running at application conditions that derate its Fmax to 400 MHz will meet or exceed the specificationsshown for Fmax = 400 MHz.Page 23 Version 2.0 9/6/2002